以電漿化學氣相沉積法製備氮化矽薄膜之二維反應器模型設計與分析

Design and analysis of two dimensional reactor model for silicon nitride fabrication by plasma enhanced chemical vapor deposition

趙廷儒(Ting-Ju Chao)

指導教授 ： 魏大欽

中原大學/工學院/化學工程學系/碩士(2022年)

https://doi.org/10.6840/cycu202201265

摘要

本研究為製備氮化矽薄膜之電漿化學氣相沉積之二維模型分析，為了解決鍍膜速率在晶圓邊緣處突然上升造成鍍膜均勻性下降的問題，建立了五種不同腔體條件的模型，再導入二維模擬，改變不同的操作參數，探討不同參數下能否改善整體鍍膜的均勻性。
首先利用本實驗室先前學長所建立的模型及反應機制，發現鍍膜速率在晶圓邊緣處會有上升的情形，造成整體鍍膜均勻性下降，推測鍍膜均勻性受上電極以及進氣盤尺寸影響，所以重新繪製新的網格模型，針對上電極和進氣盤尺寸，將模型修改成五種不同的腔體構造，主要為上電極尺寸的改變，以及進氣盤和上電極相對位置的改變。
接著將上述五種模型用CFD-ACE+進行二維的模擬，為了使模型在各種參數下能夠有相同的趨勢，因此改變氮氣、SiH4以及操作壓力，再和原始的模型進行比對，探討氣相物種濃度的二維分布和鍍膜速率分布對膜均勻性的影響，並提出增加鍍膜均勻性的方法。發現同時縮短上電極和進氣盤的尺寸能夠使整體鍍膜的均勻性提高一點，但是鍍膜速率會略為下降；而只縮小進氣盤尺寸則會發現相比於同時縮小上電極及進氣盤尺寸時的鍍膜均勻性會更大幅提升，且鍍膜速率也並沒有下降太多，由於進氣盤尺寸較小，導致擴散至出口的距離較長，所以鍍膜粒子較不容易在轉角處累積，因此可以減少鍍膜速率飆升。

關鍵字

電漿化學氣相沉積 ； 氮化矽 ； 鍍膜均勻性

並列摘要

In this study, in order to solve the problem of the deposition rate rising rapidly at the edge of the wafer and causing the uniformity to decrease, we create five different models with different boundary conditions to perform the two-dimensional simulations for different parameter values and then analyze which model can make the best uniformity.
First, after remaking the results of the senior in our laboratory, we find that the deposition rate increases at the edge of the wafer, decreasing the uniformity. We presume that the side gap is too small, causing the accumulation of deposition particles or it is related to the distance between the upper-electrode and the inlet position. As a result, we make the other four models to solve the uniformity issue.
We use CFD-ACE+ for the two-dimensional simulation. In order to make the model have the similar results in various situations, we changed the N2, SiH4 and operating pressure then compared them with the original model. It is found that by simultaneously shortening the length of the upper-electrode and the inlet position, the uniformity can actually increase a little bit, but the deposition rate will decrease slightly. We also find that by shortening the length of the inlet position only, the uniformity increases significantly, and the deposition rate does not decrease by much. We think it is because the short length of the inlet position makes the diffusion distance to the outlet position long enough and that’s why we do not see the deposition particles accumulate at the corner. From this, we can solve that the deposition rate rises rapidly at the edge.

並列關鍵字

PECVD ； SiN ； Growth uniformity

參考文獻

[1] 陳威廷, “以矽甲烷/氨氣/氮氣電漿沉積氮化矽薄膜之二維模型研究,” no. 2020年, pp. 1–104, Jan.2020, doi: 10.6840/CYCU202000618.

[2] “劉志宏, 陳志瑋, and 林春宏, "大氣壓電漿表... - Google 學術搜尋.” https://scholar.google.com.tw/scholar?hl=zh-TW&as_sdt=0%2C5&q=劉志宏%2C+陳志瑋%2C+and+林春宏%2C+%22大氣壓電漿表面改質技術與其應用介紹%2C%22+化工資訊與商情%2C+pp.+39-51%2C+2006.&btnG= (accessed Jun.28, 2022).

[3] D. (dian zi gong cheng)Zhuang and莊達人 (電子工程), “VLSI zhi zao ji shu”.

[4] D.Smith, D. H.-P.Today, and undefined1996, “Thin-film deposition: principles and practice,” ui.adsabs.harvard.edu, Accessed: Jun.28, 2022. [Online]. Available: https://ui.adsabs.harvard.edu/abs/1996PhT....49d..60S/abstract

[5] 蔡旺霖 undefined, “微晶矽薄膜製程於高頻電漿反應器之電漿診斷與模型研究,” 2011, Accessed: Jun.28, 2022. [Online]. Available: https://www.airitilibrary.com/Publication/alDetailedMesh?docid=U0017-1511201111454406