連通柱殘段對於時域反射及透射波形之分析

Analysis of Time-domain Reflection/Transmission Waveform for Via Stub

王鈺芬(YU-FEN WANG)

指導教授 ： 薛光華

中原大學/電機資訊學院/電子工程學系/碩士(2022年)

https://doi.org/10.6840/cycu202201379

摘要

在高速印刷電路板(Printed Circuit Board，PCB)之電路中，訊號連通柱(Via)已普遍作為不同佈線層訊號與訊號佈線間互連之用。最常見(最低成本)的連通柱結構為通孔(Plating Through Hole Via，PTH)，此結構會因佈線(Routing)換層間有使用帶線結構互連，其訊號連通柱將留下開路殘段(Open Stub)，而連通柱殘段(Via Stub)往往會引發訊號完整性問題。
以往至今常見的相關研究多以頻域呈現居多，然其對時域數位波形之影響較少探討，一般可以透過電磁軟體模擬得知殘段長度對於走線阻抗、接收端眼圖和插入損耗(Insertion Loss)的影響結果，並藉以判斷印刷電路板(Printed Board Circuit, PCB)是否需進行Via背鑽，但往往不知殘段對於訊號的影響及其原理。
依據上述原因，本篇將針對訊號連通柱殘段對其時域反射波形(Time-domain Reflection，TDR)與時域透射波形(Time-domain Transmission，TDT)的影響做一分析與探討。以分析圖表來協助判斷該殘段效應對於訊號品質的傷害程度是否為系統設計可承受範圍，並以電壓透射與反射原理及阻抗不連續，說明殘段長度對時域波形造成的影響。論證出利用縮短殘段長度，控制其引發之步階波平坦處的寬度，降低殘段對訊號品質的破壞，歸納出殘段長度與上升時間的關係式，作為簡易設計準則參考。

關鍵字

連通柱殘段 ； 時域反射 ； 時域透射

並列摘要

In the circuits of high speed printed circuit board (PCB), signal via has been commonly used to make interconnection between trace and trace on various routing layers. The most common signal via structure is plating through hole via (PTH), but this structure will leave an open stub due to connecting with a stripline structure while changing routing layer, and via stub often induces signal integrity problem.
From the past to now, common related research is mostly presented in the frequency domain, but its influence on the time-domain digital waveform is seldom discussed. The impact of Via stub length on trace impedance/receiving end-eye diagram/ Insertion loss can be recognized through the electromagnetic software simulation that judging whether back-drill is required. Nevertheless, the correlation of via stub about signal integrity.
As above reason, this paper will analysis and investigate the influence of signal via stub on time-domain reflection and transmission waveform. Used the analysis charts to determine the damage level of the via stub effect to the signal quality whether within the acceptable range of the system design, and based on the principe of voltage transmission and reflection and impedance discontinuity to explained about the significant for stub length will impact the signal quality as time-domain waveform. This paper demonstrated that shorten the via stub length to controlling the width of the flat part about step wave which induced by the stub, reducing the damage to the signal quality caused by the stub, and summarizing the relationship between the stub and rise time, can be used as a reference for simple design criteria.

並列關鍵字

Via Stub ； Time-domain Reflection ； Time-domain Transmission

參考文獻

[1] Stephen H. Hall, Garrett W. Hall, James A. McCall, High-Speed Digital System Design-A Handbook of Interconnect Theory and Design Practices, John Wiley & Sons, Inc., New York, 2000.

[2] Stephen H. Hall and HOWARD L.HECK, “Advanced Signal Integrity for High-Speed Digital Designs” A Wiley-Interscience Publication,2009.

[3] Ansys HFSS. [Online].Available: https://www.ansys.com/

[4] An-Yu Kuo, Xin Ai, CA Patent Application Publication –Method for circuit simulation, Sigrity Inc., US 2012/0316857 A1,Dec.13,2012.

[5] G. H. Shiue, C. L. Yeh, L. S, Liu. H, W, and W. C. Ku, “Influence and Mitigation of Longest Differential Via Stubs on Transmission Waveform and Eye Diagram in a Thick Multilayered PCB,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, no. 10, Oct 2014.