非均勻時鐘網格下時脈閘門合成技術之研究

Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering

邱奕瑄(Yi-Hsuan Chiu)

指導教授 ： 鄭維凱

中原大學/工學院/資訊工程研究所/碩士(2014年)

https://doi.org/10.6840/cycu201400909

摘要

在時脈網路設計中，時鐘網格與時鐘樹相比是個具有較高功率消耗的架構，而不均勻的時鐘網格和時脈閘門是兩種降低動態功耗常用的技術。不均勻的時鐘網格可以有效減少線長，而時脈閘門可以減少動態功率消耗。本文中，在時序約束和時脈偏移約束下，我們提出一種整合時脈閘門技術與不均勻的時鐘網格方法，降低切換電容，並且與不均勻的時鐘網格下無時脈閘門、均勻的時鐘網格下有時脈閘門做比較，實驗結果中表明我們的方法可以得到可行的解決方案，並有效地降低了切換電容。

關鍵字

不均勻時鐘網格 ； 時脈閘門

並列摘要

In the clock network synthesis, the power consumption of the clock mesh is higher than the power consumption of the clock tree, and non-uniform clock mesh and clock gating are two commonly techniques to reduce dynamic power. Non-uniform clock mesh can reduce wire length, and clock gating can reduce dynamic power consumption. In this paper, under both the enable timing constraint and clock skew constraint, we propose a methodology to reduce the switching capacitance. In comparison with no clock gating in the non-uniform clock mesh and with clock gating in the uniform clock mesh is applied, experimental results show that our methodology can get feasible solution and reduce the switching capacitance efficiently.

並列關鍵字

clock gating ； non-uniform clock mesh

參考文獻

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