應用於24GHz，60GHz與79GHz之CMOS功率放大器設計與實現

Design and Implementation of 24GHz , 60GHz and 79GHz CMOS Power Amplifiers

楊青桓(Ching-Huan Yang)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2014年)

摘要

論文摘要
本論文主要是研究利用CMOS (互補式金屬氧化物半導體)製程技術來設計與具體實現操作在24GHz，60GHz與79GHz等四顆不同頻帶之功率放大器 (Power Amplifier) ，在設計電路的過程中我們運用了ADS (Advanced Design system) 和Sonnet等軟體來為電路進行模擬，並利用Cadence Virtuoso來進行電路的佈局，最後，在委託國家晶片中心進行晶片的下線並量測。此論文的研究主軸可分成四部分：:

第一部分，我們利用0.18μm CMOS製程設計並實現了一顆應用在K頻帶之高功率附加效率的功率放大器。在電路架構方面，第一級為基本的疊接架構，第二級為基本的共源級(CS)架構來實現，主要是因為疊接架構能得到較好的增益以及改善反隔離度，線性度與功率消耗都差於共源級的架構，因此，為了取得數據上的平衡，才會第一級使用疊接的架構第二級使用共源級的架構。最後一級則是採用了Wilkinson功率分配器架構以達到輸出功率以及功率附加效率的提升。量測結果顯示此電路操作在22.5~27GHz時，增益(S21) 為17.15± 1.255dB，飽和輸出功率(Psat)為14.007dBm，最大功率附加效率(PAE)為15.359%，而電路整體消耗之功率為141.92mW，且含test pads之晶片面積為0.923 mm2。依照量測結果可以得知此電路有著不錯的特性並且適合應用於K頻帶的發射機系統。

第二部分是一個以90奈米製程實現的應用在V頻帶的高功率附加效率之功率放大器。在電路架構方面，以三級的共源級(CS)架構來實現，主要是考慮到此架構有較佳的線性度以及功耗較低的特性。量測結果顯示此電路的3-dB頻寬為9.5GHz(51~60.5GHz)，增益(S21) 為14.654 ± 0.81dB，飽和輸出功率(Psat)為7.154dBm，最大功率附加效率(PAE)為 14.87%，而電路整體消耗之功率為44.25mW，且含test pads之晶片面積則是0.611 mm2。本電路在最大功率附加效率(PAE)以及整體消耗功率上有不錯的表現。

第三部分是一個以90奈米製程實現的應用在V頻帶的高功率附加效率之功率放大器。此電路架構分成三級，前兩級以基本的共源級(CS)架構來實現，主要是考慮到此架構有較佳的線性度以及功耗較低的特性。而最後一級我們則是使用功率等分(power splitting/combining)的架構來實現，主要目的是為了要達成高輸出功率以及高功率附加效率。而與第一部分的Wilkinson功率分配器架構不同的地方是此架構可以不需要額外的電阻以減少晶片面積並且較容易完成電路級間匹配，不過在電路穩定以及對稱上則是不如Wilkinson功率分配器的架構。量測結果顯示此電路的3-dB頻寬為9GHz(57~66GHz)，增益(S21) 為9.759± 1.093dB，飽和輸出功率(Psat)為8.14dBm，最大功率附加效率(PAE)為6.54%，而電路整體消耗之功率為54.249mW，且含test pads之晶片面積則是0.657 mm2。

第四部分，我們利用90奈米CMOS製程設計了一顆應用在79GHz之高功率附加效率的功率放大器。在電路架構方面，第一級為基本的疊接架構，第二級為基本的共源級(CS)架構來實現，主要是因為疊接架構能得到較好的增益以及改善反隔離度，線性度與功率消耗都差於共源級的架構，因此，為了取得數據上的平衡，才會第一級使用疊接的架構第二級使用共源級的架構。最後一級則是採用了功率等分(power splitting/combining)的架構來以達到輸出功率以及功率附加效率的提升。量測結果顯示此電路的3-dB頻寬為6GHz(75~81GHz)，增益(S21) 為14.058± 0.555dB，飽和輸出功率(Psat)為9.847dBm，最大功率附加效率(PAE)為8.682%，而電路整體消耗之功率為85.77mW，且含test pads之晶片面積則是0.652 mm2。

關鍵字

功率放大器 ； 功率附加效率 ； 輸出飽和功率 ； K頻帶 ； V頻帶 ； 疊接 ； Wilkinson功率分配器 ； 共源級 ； 功率等分 ； 發射機

並列摘要

Abstract
The purpose of this paper is to research into design and achieve different frequency band of power amplifier which operated in 24GHz, 60GHz and 79GHz by CMOS (Complementary Metal-Oxide-Semiconductor) process technology. In the circuit design process, we use softwares of ADS (Advanced Design system) and Sonnet to simulate the circuit and use Cadence Virtuoso to layout circuit, finally, the fabrication and measurement of the PA (Power Amplifier) in this paper are supported by CIC. The thesis can be divided into four parts：
The first part is on the design and implement of a high added efficiency power amplifier for K-band applications in 0.18μm CMOS technology. In this circuit, we used the cascade-stage structure as first stages to eliminate the Miller effect and improve the reverse isolation. The second stage is using common source topology. In the cause of improving the output power and power added efficiency, we use the Wilkinson power divider/combiner to implement final stage. The measured results show that this circuit operating on 22.5~27GHz, the gain (S21) is 17.15± 1.255dB, saturation output power (Psat) is 14.007dBm, max power added efficiency (peak PAE) is 15.359%, total power consumption is 141.92mW and the chip area (including test pads) is 0.923mm2. These results indicate that this circuit performs well and is suitable for K-band transmitter systems.
The second part is on the design and implement of a high added efficiency power amplifier for V-band applications in 90nm CMOS process. In this circuit, the three stages are implemented with single device common-source topology, which have better linearity and lower power consumption. The measured results show that 3-dB bandwidth of this power amplifier is 9.5GHz (51~60.5GHz), gain (S21) is 14.654± 0.81dB, saturation output power (Psat) is 7.154dBm, max power added efficiency (peak PAE) is 14.87%, total power consumption is 44.25mW and the chip area (including test pads) is 0.611mm2. This circuit performs well in power added efficiency (PAE) and total power consumption.
The third part is on the design and implement of a high added efficiency power amplifier for V-band applications in 90nm CMOS process. This circuit could be divided into three stages. The first two stages are implemented with single device common-source topology, which have better linearity and lower power consumption. In order to achieve the higher output power and higher power added efficiency, the technique of power splitting/combining is used in final stage. Not like the Wilkinson power divider/combiner in the first part. This structure need not have added resistors. So the chip area could be saved and it is easy to achieve inter-stage matching. But in stability and symmetry of structure, this power splitting/combining structure is worse than Wilkinson power divider/combiner. The measured results show that 3-dB bandwidth of this power amplifier is 9GHz (57~66GHz), gain (S21) is 14.058± 0.555dB, saturation output power (Psat) is 8.14dBm, max power added efficiency (peak PAE) is 6.54%, total power consumption is 54.249mW and the chip area (including test pads) is 0.657mm2.
The four part is on the design and implement of a high added efficiency power amplifier for 79GHz applications in 90nm CMOS technology. In this circuit, we used the cascade-stage structure as first stages to eliminate the Miller effect and improve the reverse isolation. But linearity and power consumption are worse than common source stage. Therefore, the second stage is using common source topology. In the cause of improving the output power and power added efficiency, we use the power divider/combiner to implement final stage. The measured results show that this circuit operating on 75~81GHz, the gain (S21) is 14.058± 0.555dB, saturation output power (Psat) is 9.847dBm, max power added efficiency (peak PAE) is 8.682%, total power consumption is 88.77mW and the chip area (including test pads) is 0.652mm2.

並列關鍵字

power amplifier (PA) ； power added efficiency (PAE) ； saturation output power(Psat) ； K-band ； V-band ； cascode ； Wilkinson power divider/combiner ； common source (CS) ； power spitting/combining ； transmitter

參考文獻

References

[1] CIC訓練課程(C604), “Power Amplifier Design and Simulation using ADS:

Training Manual”, pp.54, July-2010

[2] 陳科后(2004).The Design and Implementation of Power Amplifier, Low Noise Amplifier and Wideband Amplifier. Unpublished master dissertation, National Chi-Nan

University, Taiwan.