低功率可調變式快速傅立葉轉換處理器之超大積體電路設計

VLSI Design of Low Power Reconfigurable Fast Fourier Transform Processor

張鴻毅(Hung-Yi Chang)

指導教授 ： 吳俊德

國立暨南國際大學/科技學院/電機工程學系/碩士(2009年)

https://doi.org/10.6837/NCNU.2009.00089

摘要

本篇論文提出一顆低功率可調變式快速傅立葉轉換處理器的晶片。此種快速傅立葉轉換處理器皆可應用於語音訊號辨識、影像處理和通訊系統之使用。以正交分頻多工的通訊系統來說，計算量大且低功率的快速傅立葉轉換(Fast Fourier Transform)處理器扮演一個重要的角色。在這篇論文，我們主要的貢獻為可調變式快速傅立葉轉換處理器。在可調變式快速傅立葉轉換處理器的設計上，為了降低晶片的功率消耗，我們改採用in-place mode記憶體架構，此記憶體架構較暫存器陣列架構更低功率。可調變式快速傅立葉轉換處理器的晶片使用UMC 90nm 標準單元(standard cell)合成出處理器電路，FFT/IFFT處理器晶片面積約為4.41mm2，gate count約為318818，根據不同的FFT點數latency 時間分別約為0.64/2.96/14.16/66.64μs，最高工作頻率為50MHz。

關鍵字

可調變 ； 快速傅立葉轉換

並列摘要

This paper proposed a low power reconfigurable FFT processor. The FFT processor can be widely used in speech recognition, image process and communication system. In orthogonal frequency-division multiplexing (OFDM) system, a high throughput rate and low power FFT processor plays an important role. In this paper, we adopt in-place mode of memory architecture to reduce power consumption. The power of the memory architecture is less than register array structure. The FFT/FFT chip is synthesized by UMC 90nm standard cell library. The die size of the FFT/IFFT processor is approximately 4.41mm2. The gate count of FFT/IFFT chip is about 318818. According to different FFT point, the latency is about 0.64/2.96/14.16/66.64μs. The maximum frequency of the chip is 50MHz.

並列關鍵字

Reconfigurable ； FFT

參考文獻

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