W頻帶CMOS收發機關鍵電路之設計

Design of Key Components of W-Band CMOS Transceiver

王建今(Chien-Chin Wang)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/博士(2017年)

摘要

本論文以W頻帶CMOS收發機之關鍵子電路為研究目標。此論文主要分為三個部分。首先，我們以TSMC 90 nm CMOS製程設計了一個利用微型Dual-Y-Shaped功率結合器及RL負載之 94 GHz功率放大器。接下來，我們以TSMC 90 nm CMOS製程技術設計了兩個分別使用負電阻補償及修正導數疊加技術之94 GHz升頻混波器。最後，我們以TSMC 90 nm 製程CMOS技術設計了設計了一個94 GHz降頻混波器。
首先，我們提出一個應用於雷達感測器之94 GHz四路功率放大器。其包含一個具寬頻pi匹配輸入/輸出網路之二級串接共源極放大器，一個使用Y型功率結合器/分配器之二路疊接放大器，及一個使用雙重Y型功率結合器/分配器之四路共源極輸出級。低損耗之雙重Y型功率結合器對後級串接RL負載進行阻抗轉換，以得到最佳的輸出功率及功率附加效率(PAE)。功率增益在71 GHz、77 GHz及94 GHz分別達到19.8、21.8及14 dB，最大輸出功率分別為10.8、10.7及7.2 dBm，而最大PAE分別為13.6％、12.5％及7.1％。此CMOS功率放大器在V頻帶及W頻帶的整體表現相當出色。
接下來我們提出了一個W頻帶升頻混波器。其包含一個具有PMOS負電阻補償以提升轉換增益之增強型雙平衡式吉勃特單元，將單端LO輸入訊號轉為差動訊號之馬遜巴倫及將差動RF輸出訊號轉為單端訊號之馬遜巴倫，及一個抑制負載效應之輸出緩衝放大器。其功率消耗為6.9 mW。RF頻率為90~100 GHz時，LO端及RF端的輸入損耗分別為-17.8~ -38.7 dB及-16.8~ -27.9 dB。最大轉換增益3.6 dB發生在RF頻率為95 GHz。RF頻率為91.9~99.4 GHz時，轉換增益為2.1±1.5 dB，相對應RF的3 dB頻寬為7.5 GHz。而RF頻率為94 GHz的LO-RF隔離度為36.8 dB。在最近幾篇94 GHz CMOS/BiCMOS升頻混波器的文獻中，我們具有最佳的轉換增益、LO-RF隔離度及功率消耗。
緊接著是一個使用負電阻補償及修正導數疊加技術之94GHz升頻混波器。其包含一個具有PMOS負電阻補償以提升轉換增益之增強型雙平衡式吉勃特單元，一個具修正導數疊加以提高線性度的轉導級，及一個抑制負載效應之輸出緩衝放大器。其功率消耗為8.5 mW。LO端及RF端的輸入損耗在RF頻率分別為81.4~110 GHz及33.8~105.5 GHz時均低於-10 dB。最大轉換增益3.6 dB發生在RF頻率為97 GHz。RF頻率為77.5~100.2 GHz時，轉換增益為2.1±1.5 dB，相對應RF的3 dB頻寬為22.7 GHz。而RF頻率為94 GHz的LO-RF隔離度為41.3 dB。在最近幾篇W頻帶升頻混波器的文獻中，我們具有最佳的轉換增益、LO-RF隔離度、功率消耗及匹配頻寬。
最後，我們提出了一個94GHz的降頻混波器。其使用了負電阻補償技術也就是基於PMOS LC振盪器之轉導級負載，用來增加RF轉導級的輸出阻抗及抑制其回授電容Cgd，改善了轉換增益、雜訊指數及LO-RF隔離度。功率消耗為6.3 mW。RF頻率為80~100 GHz時，RF端及LO端的輸入損耗分別為-8.7~ -22 dB及-10.3~ -19.4 dB，轉換增益為4.1~ 11.6 dB，雜訊指數為15.8~18.1 dB，LO-RF隔離度為42.1~54 dB。在最近幾篇W頻帶CMOS降頻混波器的文獻中，我們具有最佳的轉換增益、雜訊指數及LO-RF隔離度。

關鍵字

功率放大器 ； 雙重Y型功率結合器 ； 串接RL負載 ； 功率附加效率 ； 輸出功率 ； 雙平衡式 ； 升頻混波器 ； 轉換增益 ； 隔離度 ； 電流注入 ； 負電阻補償 ； 輸出緩衝放大器 ； 修正導數疊加 ； 降頻混波器 ； LC振盪器

並列摘要

This thesis focuses on the design of key components of W-band CMOS transceiver. This thesis is divided into three parts. Firstly, A four-way 94 GHz power amplifiers (PA) using miniature dual Y-shaped combiner with RL load for radar sensors in 90 nm CMOS technology is reported. Secondly, we reports two 94GHz up-conversion mixer using PMOS negative resistance compensation (NRC) and simplified modified derivative superposition (MDS) respectively in 90 nm CMOS technology. Finally, A 94 GHz CMOS down-conversion mixer using PMOS LC-oscillator-based RF transconductance (GM) stage load in 90 nm CMOS technology is presented.
First of all, we reports a four-way 94 GHz power amplifiers (PA) for radar sensors in 90 nm CMOS technology. The PA comprises a two-stage common-source (CS) cascaded input stage with wideband pi-match input, inter-stage and output networks, followed by a two-way cascode gain stage using Y-shaped divider and combiner, and a four-way CS output stage using dual Y-shaped divider and combiner. At each branch’s input terminal (i.e. drain terminal of the parallel CS output stage), the low-loss dual Y-shaped combiners can convert the serial RL load to the impedance for optimal output power (Pout) and power-added efficiency (PAE). The PA achieves power gain of 19.8, 21.8 and 14 dB, respectively, at 71, 77 and 94 GHz. In addition, the PA achieves Pout of 10.8, 10.7 and 7.2 dBm, respectively, at 71, 77 and 94 GHz. The corresponding peak PAE is 13.6%, 12.5% and 7.1%, respectively, at 71, 77 and 94 GHz. The overall performance of the CMOS PA is remarkable in V-band and W-band.
The second, a W-band double-balanced mixer for direct up-conversion using standard 90 nm CMOS technology is reported. The mixer comprises an enhanced double-balanced Gilbert cell with PMOS negative resistance compensation (NRC) for conversion gain (CG) enhancement and current injection for power consumption reduction and linearity improvement, a Marchand balun for converting the single LO input signal to differential signal, another Marchand balun for converting the differential RF output signal to single signal, and an output buffer amplifier for loading effect suppression, power consumption reduction and CG enhancement. The mixer consumes low power of 6.9 mW and achieves LO-port input reflection coefficient of -17.8~ -38.7 dB and RF-port input reflection coefficient of -16.8~ -27.9 dB for frequencies of 90~100 GHz. The mixer achieves maximum CG of 3.6 dB at 95 GHz, and CG of 2.1±1.5 dB for frequencies of 91.9~99.4 GHz. That is, the corresponding 3 dB CG bandwidth is 7.5 GHz. In addition, the mixer achieves LO-RF isolation of 36.8 dB at 94 GHz. To the authors’ knowledge, the CG, LO-RF isolation and power dissipation results are the best data ever reported for a 94 GHz CMOS/BiCMOS up-conversion mixer.
Then, a 94 GHz double-balanced mixer for direct up-conversion using 90 nm CMOS technology is reported. The mixer adopts an enhanced double-balanced Gilbert cell with PMOS negative resistance compensation (NRC) for conversion gain (CG) enhancement and simplified modified derivative superposition (MDS) in the transconductance stage for linearity improvement. In addition, an output buffer amplifier is included for loading effect suppression, CG enhancement and power consumption reduction. The mixer consumes 8.5 mW and achieves LO-port and RF-port input reflection coefficient better than 10 dB for frequencies of 81.4~110 GHz and 33.8~105.5 GHz, respectively. The mixer achieves maximal CG of 3.6 dB at 97 GHz, and CG of 2.1±1.5 dB for frequencies of 77.5~100.2 GHz. That is, the corresponding 3 dB CG bandwidth is 22.7 GHz. In addition, the mixer achieves LO-RF isolation of 41.3 dB at 94 GHz. To the authors’ knowledge, the CG, LO-RF isolation, power dissipation and matching bandwidth results are one of the best data ever reported for a W-band up-conversion mixer.
Last, A 94 GHz CMOS down-conversion mixer is reported. RF negative resistance compensation (NRC) technique, i.e. PMOS LC-oscillator-based RF transconductance (GM) stage load, is used to increase the output impedance and suppress the feedback capacitance Cgd of RF GM stage. As a result, conversion gain (CG), noise figure (NF) and LO-RF isolation of the mixer are enhanced. For frequencies of 80~110 GHz, the mixer consumes 6.3 mW and achieves excellent RF-port input reflection coefficient (S11) of -8.7~ -22 dB and LO-port input reflection coefficient (S22) of -10.3~ -19.4 dB. In addition, the mixer achieves excellent CG of 4.1~11.6 dB, NF of 15.8~18.1 dB, and LO-RF isolation of 42.1~54 dB for frequencies of 80~110 GHz, one of the best CG, NF and LO-RF isolation results ever reported for a W-band CMOS down-conversion mixer.

並列關鍵字

power amplifier ； dual Y-shaped combiner ； serial RL load ； power added efficiency (PAE) ； output power ； double-balanced ； up-conversion mixer ； conversion gain ； isolation ； current injection ； negative resistance compensation ； output buffer amplifier ； simplified modified derivative superposition ； down-conversion mixer ； LC-oscillator

參考文獻

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[1.2] C. S. Wang, J. W. Huang, K. D. Chu, and C. K. Wang, "A 0.13 μm CMOS fully differential receiver with on-chip baluns for 60 GHz broadband wireless communications," 2008 IEEE CICC, pp. 479-482.

[1.3] F. Zhang, E. Skafidas, and W. Shieh, "A 60-GHz double-balanced Gilbert cell down-conversion mixer on 130 nm CMOS," 2007 IEEE RFIC Symposium, pp. 141-144.

[1.4] V. Jain, F. Tzeng, L. Zhou, and P. Heydari, "A Single-Chip Dual-Band 22-29-GHz/77-81-GHz BiCMOS Transceiver for Automotive Radars," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3469-3485, Dec. 2009.

[1.5] W. L. Chan and J. R. Long, “A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply,” IEEE Journal of Solid-State Circuits, vol.45, no. 3, pp. 554-564, 2010.