超寬頻帶和V頻帶CMOS接收機前端電路之研究

Study of Ultra-Wideband and V-band CMOS Receiver Front-End

李仁豪(Jen-How Lee)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/博士(2013年)

https://doi.org/10.6837/NCNU.2013.00314

摘要

本論文以超寬頻帶和V頻帶CMOS接收機前端電路為研究目標。此論文主要分為三大部分。首先，我們以TSMC 90-nm CMOS製程技術實現了3-20-GHz低雜訊放大器、3-20-GHz接收器前端電路。接下來，我們以TSMC 0.18-?m CMOS製程技術實現了一個21-29-GHz接收機前端電路。最後,我們以TSMC 90-nm CMOS製程技術實現了50.4-62.9-GHz寬頻低雜訊放大器、60-GHz雙平衡式混頻器以及60-GHz接收機前端電路。
首先,我們提出一個電流再生串接組態的寬頻低雜訊放大器。其利用電阻並並回授，搭配負載並聯LC形成一個二階寬頻帶通濾波器，來實現寬頻輸入匹配。總功率消耗為9.96毫瓦，且於1.9 GHz到22.5 GHz範圍內，輸入反射係數低於–8.77 dB，隔離度低於–29.7 dB，順向增益11.52±2 dB和4.24±0.65 dB的雜訊指數；除此之外，輸出反射係數在2.6 GHz到26.5 GHz範圍內都低於–10 dB。
緊接著是一個由電流再生串接式的低雜訊放大器、單平衡式混波器和將差動輸出轉單端輸出的轉換器所組成的3–20-GHz寬頻融合LNA和Mixer之接收機前端電路。其具有14.01±2.63 dB的轉換增益、RF端的輸入反射係數低於–8.77 dB、LO-IF的隔離度低於–29.9 dB、LO-RF的隔離度低於–43.4 dB、RF-IF的隔離度低於–60.1 dB；並且在4 GHz時，具有最小的雜訊指數3.46 dB。此電路包含測試墊的面積為0.985 mm2，總功率消耗為9.2毫瓦。
接下來我們提出了一個21-29 GHz互補式金氧半導體超寬頻接收機前端電路，包含一個低雜訊放大器、一個波混頻器及二個馬遜巴倫。 此接收機前端電路具有4.6±0.5 dB的雜訊指數、23.7±1.4 dB的轉換增益、RF端輸入損耗低於–8.8 dB、LO-IF的隔離度低於–47 dB、LO-RF的隔離度低於–55 dB和低於–35.5 dB的RF-IF隔離度。此電路包含測試墊的面積為1.25?1.06 mm2，總功率消耗為39.2毫瓦。
然後是一個具有9.92±1.5 dB 順向增益和最小雜訊指數3.88 dB 的14.1毫瓦之50.4-62.9 GHz三級低雜訊放大器。其輸入損耗在55.1 GHz 到 59.5 GHz之間低於–10 dB和輸出損耗在55.1 GHz 到 59.4 GHz之間低於–10dB。在3-dB頻寬內的隔離度低於–42.6 dB，並且在60 GHz的P1dB和IIP3分別是–23 dBm和–11.2 dBm。此電路包含測試墊的面積為0.58 mm2。
除此之外，我們也提出了一個60-GHz直接降頻式雙平衡式混波器。由一個具有電流再生的RF端單端轉雙端輸出之轉換器、LO端整合馬遜巴倫之雙平衡式吉伯特混波器和基頻放大器組合而成。在60-GHz時，雜訊指數為12.8 dB，總功率消耗為17毫瓦。在RF頻率為60 GHz和LO頻率為59.9 GHz時，其LO-RF隔離度為–64.7 dB、LO-IF隔離度為–51.5 dB和RF-IF隔離度為–59.5 dB。在IF頻率固定為0.1 GHz時，最大的轉換增益15.46 dB發生在RF頻率為62 GHz，而RF頻率為60 GHz的轉換增益為14.7 dB，在最近幾篇60 GHz混波器的文獻中，我們具有最佳的轉換增益。
最後，60-GHz接收機前端電路包含寬頻低雜訊放大器、具有電流再生的RF端單端轉雙端輸出之轉換器和LO端整合馬遜巴倫之雙平衡式吉伯特混波器和基頻放大器組合而成，總消耗之功率為34.36毫瓦，且於RF頻率為60 GHz和LO頻率為59.9 GHz的LO-RF、LO-IF和RF-IF隔離度分別為?60.7 dB、?45.3 dB和?41.9 dB。在IF頻率固定為0.1 GHz時，最大的轉換增益26.1 dB發生在RF頻率為64 GHz，而RF頻率為60 GHz的轉換增益為25.2 dB，相對應RF的3-dB頻寬為7.26 GHz(58.39 GHz 到 65.65 GHz)。而最小雜訊指數8.1 dB在RF頻率為65 GHz。這些結果暗示著我們的60-GHz接收機前端電路在射頻積體電路的應用上是非常有潛力的。

關鍵字

超寬頻 ； 60-GHz ； V-band ； 低雜訊放大器 ； 單平衡式混頻器 ； 雙平衡式混頻器 ； 接收機前端電路 ； 馬遜巴倫 ； 單端轉雙端轉換器 ； 電流再生技術

並列摘要

The aim of this thesis is to design the ultra-wideband and V-band front-end circuits of CMOS receivers. This thesis is divided into three parts. First, a 3-20-GHz low-noise amplifier (LNA) and a 3-20-GHz CMOS receiver front-end were implemented by TSMC 90-nm CMOS technology. Second, a 21-29-GHz CMOS receiver front-end was implemented by TSMC 0.18-?m CMOS technology. Finally, a 57.9-66.4-GHz wideband LNA, a 60-GHz double-balanced mixer, and a 60-GHz receiver front-end were implemented by TSMC 90-nm CMOS technology.
First of all, a wideband LNA based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt–shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel-branches, i.e., a second-order wideband bandpass filter. This LNA dissipates 9.96 mW power and achieves S11 below –8.77 dB, S12 below –29.7 dB, S21 of 11.52±2 dB, and flat NF of 4.24±0.65 dB over the 1.9–22.5-GHz band of interest. Besides, S22 below –10 dB from 2.6 to 26.5 GHz is also achieved.
Second, a 3–20-GHz wideband merged CMOS LNA and Mixer comprises a current-reused cascaded LNA, a single-balanced (SB) mixer and a differential to single converter (DSC) for converting differential IF signal to single signal and wideband output matching. The proposed merged LNA and SB mixer exhibits a conversion gain of 14.01±2.63 dB, RF port reflection coefficient lower than –8.77 dB, LO-IF isolation lower than –29.9 dB, LO-RF isolation lower than –43.4 dB, RF-IF isolation lower than –60.1 dB, and a minimum noise figure (NFmin) of 3.46 dB at 4 GHz. This circuit occupies a chip area of 0.985 mm2, including the test pads. The total dc power dissipation is only 9.2 mW.
Then, we present a 21-29 GHz CMOS UWB receiver front-end. The receiver front-end comprises a low-noise amplifier (LNA), a mixer, and two Marchand baluns. Over the 21-29 GHz band, the receiver front-end exhibits excellent NF of 4.6±0.5 dB, conversion gain of 23.7±1.4 dB, RF port reflection coefficient lower than –8.8 dB, LO-IF isolation lower than –47 dB, LO-RF isolation lower than –55 dB, and RF-IF isolation lower than –35.5 dB. The circuit occupies a chip area of 1.25?1.06 mm2, including the test pads. The dc power dissipation is only 39.2 mW.
A 50.4-62.9 GHz three-stage LNA exhibits forward gain (S21) of 9.92±1.5 dB and a minimum noise figure (NFmin) of 3.88 dB at 55.5 GHz with power consumption of 14.1 mW. The measured S11 was better than –10 dB from 55.1 GHz to 59.5 GHz and S22 was better than –10 dB from 55.1 GHz to 59.4 GHz. The measured reverse isolation S12 is better than –42.6 dB over the 3-dB bandwidth. It also achieved P1dB-in of –23 dBm, and IIP3 of –11.2 dBm at 60 GHz. The chip size of this LNA is 0.58 mm2 including all the testing pads.
In addition, a 60 GHz double-balanced mixer for direct down-conversion is reported. The down-conversion mixer comprises a double-balanced Gilbert cell with a current-reused RF single-to-differential converter (SDC) for conversion gain (CG) enhancement, a Marchand balun for converting the single LO input signal to differential signal, and a baseband amplifier. The mixer consumes 17 mW and achieves low noise figure (NF) of 12.8 dB at 60 GHz. In addition, the mixer achieves excellent LO-RF isolation of –64.7 dB, LO-IF isolation of –51.5 dB, and RF-IF isolation of –59.5 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 0.1 GHz, the mixer achieves maximum CG of 15.46 dB at RF of 62 GHz, and CG of 14.7 dB at RF of 60 GHz, the best CG results ever reported for a 60 GHz CMOS down-conversion mixer.
Finally, the 60-GHz receiver front-end comprises a wideband low-noise amplifier (LNA), a double-balance Gilbert cell mixer with current-reused RF single-to-differential converter (SDC), a marchand balun and a baseband amplifier. The receiver front-end consumed 34.36 mW and achieved LO-RF isolation of ?60.7 dB, LO-IF isolation of ?45.3 dB, and RF-IF isolation of ?41.9 dB at RF of 60 GHz and LO of 59.9 GHz. At IF of 100 MHz, the receiver front-end achieved maximum conversion gain of 26.1 dB at RF of 64 GHz and CG of 25.2 dB at RF of 60 GHz. The corresponding 3-dB bandwidth (?3dB) of RF is 7.26 GHz (58.39 GHz to 65.65 GHz). The measured minimum noise figure (NF) was 8.1 dB at 65 GHz, an excellent result for a 60-GHz-band CMOS receiver front-end. These results demonstrate the adopted receiver front-end architecture is very promising for high-performance 60-GHz-band RFIC applications.

並列關鍵字

ultra-wideband ； 60-GHz ； V-band ； low-noise amplifier (LNA) ； single-balanced mixer ； double-balanced mixer ； receiver front-end ； marchand balun ； single-to-differential converter (SDC) ； current-reused technique

參考文獻

[1] C. Park and T.S. Rappaport, “Short-range wireless communications for next-generation networks: UWB, 60 GHz millimeter-wave WPAN, and ZigBee,” IEEE Wireless Communication., vol. 14, pp. 70-80, Aug. 2007.

[2] V. Jain, F. Tzang, Lei Zhou, and P. Heydari, “A Single-Chip Dual-Band 22–29-GHz/77–81-GHz BiCMOS Transceiver for Automotive Radars,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3469–3485, Dec. 2009.

[3] M. Q. Chen, W. Sutton, I. Smorchkova, B. Heying, W. B. Luo, V. Gambin, F. Oshita, R. Tsai, M. Wojtowicz, R. Kagiwada, A. Oki, and J. S. Lin, “A 1–25 GHz GaN HEMT MMIC Low-Noise Amplifier,” IEEE Microwave Wireless Comp. Letter, vol. 20, no. 10, pp. 563-565, Oct. 2010.

[4] D. C. Howard, J. Poh, T. S. Mukerjee, and J. D. Cressler, “A 3–20 GHz SiGe HBT ultra-wideband LNA with gain and return loss control for multiband wireless applications,” 2010 IEEE Midwest Symposium on Circuits and Systems, 2010, pp. 445-448.

[5] P. K. Saha, S. Shankar, R. Schmid, R. Mills, and J. D. Cressler, “Analysis and design of a 3–26 GHz low-noise amplifier in SiGe HBT technology,” 2012 IEEE Radio and Wireless Symposium, 2012, pp. 203-206.