配電網絡設計方法為了加速實體設計的完成

Power-Distribution-Network Design Methodologies toward Fast Physical-Design Closure

張玟翔(Wen-Hsiang Chang)

指導教授 ： 趙家佐

國立交通大學/電機學院/電子工程系所/博士(2018年)

摘要

隨著製程持續進步和設計複雜度持續增加，配電網絡(PDN)需要更多的繞線資源來滿足IR-drop和EM限制。在本論文中我們首先提出一個設計流程，用來在放置之前建立一個對繞線友善的PDN。這個設計流程考慮AP層的影響和PDN佈局配置的影響。接者，我們提出一個動態規劃的方法，用來最小化一個給定的均勻擺放的PDN在繞線上的影響，藉由在放置之後調整電源線的位置。實驗結果操作在40nm的微處理器上，顯示提出的設計流程和提出的動態規劃的方法，可以有效的產生一個對繞線友善的PDN，從而加速實體設計的完成。最後，我們提出一個設計流程，用來在放置之後，產生一個會讓全域/細部繞線總長差不多最小的PDN。此設計流程使用一個機器學習的模型，來快速的預測在給定一個PDN佈局配置下，其全域繞線的總長。實驗結果操作在28nm的工業設計上，顯示提出的設計流程，可以有效的產生一個對繞線友善的PDN，從而加速實體設計的完成。

關鍵字

配電網絡 ； 機器學習 ； 繞線成本模型 ； 電源網絡設計 ； 電遷移效應 ； 繞線驅策 ； 壓降 ； 配電網絡設計 ； 元件壓降

並列摘要

As technology node keeps scaling and design complexity keeps increasing, power distribution network (PDN) require more routing resource to meet IR-drop and EM constraints. In this thesis, we first presented a design flow to build a routing-friendly PDN before placement. The design flow considers the impact of the aluminum-pad layer and the impact of PDN layout configurations. Second, we proposed a dynamic programming (DP) approach to further minimize the routing impact of a given uniform PDN by relocating the power stripes after placement. The results based on a 40nm microprocessor demonstrate that the proposed design flow and the proposed DP approach can effectively generate a routing-friendly PDN and in turn speed up the design closure at the physical-design stage. Finally, we propose a design flow to generate a PDN that can result in a near-minimal total wire length of global route (and in turn detailed route as well) after placement. The design flow uses a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration. Experiment results based on 28nm industrial block designs demonstrate that the proposed design flow can generate a routing-friendly PDN and in turn speed up the design closure at the physical-design stage.

並列關鍵字

power distribution network ； PDN ； Machine-Learning ； routing cost model ； power grid design ； EM ； routing-driven ； Electromigration ； IR drop ； PDN design ； instance IR drop

參考文獻

[1] H. Qian, S. Nassif, and S. Sapatnekar, “Random walks in a supply network,” in Design Automation Conference, 2003. Proceedings, June 2003, pp. 93–98.

[2] B. Boghrati and S. Sapatnekar, “Incremental power network analysis using backward random walks,” in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, Jan 2012, pp. 41–46.

[3] H. Qian and S. Sapatnekar, “A hybrid linear equation solver and its application in quadratic placement,” in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, Nov 2005, pp. 905–909.

[4] T.-H. Chen and C. Chen, “Efficient large-scale power grid analysis based on pre-conditioned krylov-subspace iterative methods,” in Design Automation Conference, 2001. Proceedings, 2001, pp. 559–562.

[5] E. Chiprout, “Fast fl hip power grid analysis via locality and grid shells,” in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, Nov 2004, pp. 485–488.