金屬與N型4H-碳化矽接面特性之研究

A Study on Contact Characteristics of Metal and n-Type 4H-Silicon Carbide

鄭嶸健(Jung-Chien Cheng)

指導教授 ： 崔秉鉞

國立交通大學/電機學院/電子工程系所/博士(2018年)

摘要

近年來，能源議題成為了眾所矚目的議題。有效率的能源轉換更是達成節能減碳的重點。相較於傳統矽基功率元件，以寬能隙材料(wide bandgap material)作為基材能夠大幅提升操作額定電壓，並降低操作中的功率損耗。其中，由於4H-碳化矽具備高導熱係數，更令其多了適用於嚴苛高溫環境的優點，也被普遍認為是新世代的功率半導體主流材料。然而，高價的磊晶基板及多項特殊製程步驟，均提高了生產成本，使得碳化矽功率元件仍不能廣泛取代傳統矽基功率元件。本研究團隊的目標是於N型4H-碳化矽基板上發展出一套可控蕭基位障高度(Schottky barrier height)的金半接面製程，並衍伸用於降低歐姆接觸(ohmic contact)之特徵接觸阻抗(specific contact resistance)。
在本論文當中，將介紹吾人為控制金半接面之蕭基位障所開發的各種表面處理製程，包括介電質夾層製程、感應耦合氬氣電漿處理(Ar ICP treatment)與快速熱退火處理(rapid thermal annealing)。藉由控制金屬沈積後退火(post-metal-deposition annealing)的溫度條件，可以精準鎖定蕭基位障高度，並有效減少元件間的變異量。同時，造成蕭基位障高度調變的機制將會在本論文中作一全面探討。
在歐姆接觸的研究方面，吾人根據蕭基位障高度的改變，將各種表面處理製程應用於歐姆接觸的製作上，以求降低特徵接觸阻抗並元件操作時的功率損耗。吾人率先提出藉由感應耦合氬氣電漿處理及600 ℃金屬沈積後退火，可於N型重摻雜4H-碳化矽上，達成最低特徵接觸阻抗僅有8.3×10-7 Ω-cm2的歐姆接觸。研究結果顯示，相較於昂貴的高溫離子佈植製程，一般室溫下離子佈植形成具缺陷的N型重摻雜層更有利於降低特徵接觸阻抗，同時減少製程的生產成本。且較低的金屬沈積後熱預算可使介面形貌較為平緩，有利於歐姆接觸的可靠度。
在本研究團隊先前的研究中，已經證實經由一道預非晶化佈值(pre-amorphization implantation)，碳化矽的局部氧化技術(LOCal Oxidation on SiC, LOCOSiC)是可行的。吾人藉金半接面及接面二極體的電流-電壓特性對場氧化層品質十分敏感的特點，用以驗證其應用於元件絕緣時，相對於電漿輔助化學氣相沈積(PECVD)氧化層，對活性區元件可能造成的影響。研究結果顯示，因碳化矽局部氧化平緩的表面形貌及品質較佳的熱氧化層，緩解了電場集中的效應，壓制漏電流及早期崩潰的發生。然而，碳化矽局部氧化的條件仍需進一步優化，以避免預非晶化的區域再結晶，造成不可預期的劣化。

關鍵字

碳化矽功率元件 ； 蕭基二極體 ； 歐姆接觸 ； 感應耦合氬氣電漿處理 ； 費米能階鎖定 ； 碳化矽局部氧化隔離技術

並列摘要

Recently, the supply and demand of power become an attractive issue. Elevating the power transfer efficiency is one of the most important factors for power saving and carbon reduction. Compared with the traditional Si-based power devices, using the wide bandgap semiconductors as the starting material can raise the blocking voltage rating and reduce the power loss during device operation. Among the wide bandgap semiconductors, 4H-SiC is generally considered as a candidate for the next-generation power device. Furthermore, the high thermal conductivity of 4H-SiC is beneficial for high-temperature and high-current applications. However, the high costs of epitaxial substrates and special fabrication processes is the bottleneck for replacement of Si-based power devices. The goal of our research is to develop a fabrication process of metal-semiconductor contact containing a controllable Schottky barrier height. Meanwhile, this fabrication process can reduce specific contact resistance of the ohmic contact according to the Schottky barrier height modulation.
In this dissertation, several surface treatments applied on the n-type Schottky contact are developed, including dielectric layer insertion, Ar inductively coupled plasma treatment, and rapid thermal annealing. The Schottky barrier height can be precisely pinned at a certain level by different post-metal-deposition annealing temperatures. The device-to-device deviation can be minimized at the same time. The mechanism of Schottky barrier height modulation is studied by electrical characterization and material analyses.
According to the Schottky barrier modulation, those surface treatments were applied on the ohmic contacts for the reduction of specific contact resistance. The specific contact resistance of the ICP-treated Ti ohmic contacts on room-temperature-implanted n+-SiC after 600 ℃ post-metal-deposition annealing is 8.3×10-7 Ω-cm2, which is the lowest value in this dissertation. This result suggests that the ohmic contact can be formed by room-temperature implantation, which is more economic than general high-temperature implantation. Besides, the low post-metal-deposition thermal budget results in a smoother morphology of the metal-semiconductor interface, which is beneficial for contact reliability.
Based on the former study of our research group, the feasibility of LOCOSiC process with an Ar ion pre-amorphization implantation is proofed. We have verified the impact on the metal-semiconductor contact and n+/p junction diode, which are sensitive to the quality of field oxide grown by LOCOSiC process or deposited by PECVD. Compared with the PECVD-oxide-isolated diodes, the smoother edge profile and the better oxide quality of LOCOSiC isolation are beneficial for high-power electronics to suppress the leakage current and prevent immature breakdown without edge termination. However, the parameters of LOCOSiC process have to be optimized to prevent the recrystallization of pre-amorphized SiC and the unpredictable degradation.

並列關鍵字

SiC power device ； Schottky barrier diode ； Ohmic contact ； Ar inductively coupled plasma treatment ； Fermi-level pinning ； Local oxidation of SiC

參考文獻

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