具正交相位輸出之低電壓操作同步複製延遲電路

A Low Supply Voltage Synchronous Mirror Delay with Quadrature Phase Output

許智勛(Chih-hsun Hsu)

指導教授 ： 鄭國興

國立中央大學/資訊電機學院/電機工程學系/碩士(2012年)

摘要

摘 要
本論文提出一個具正交相位時脈輸出之低電壓操作同步複製延遲電路晶片設計。此
電路將在前3 個週期執行粗調動作，爾後的8 個週期完成細微調整，藉由兩階段的調整
達到時脈同步的功能。細微調整可以進一步降低同步時脈的靜態相位誤差，並且採用環
形動態調整機制，能夠讓時脈在同步後，仍能保有動態追鎖的校正功能。另外，透過兩
階段邊緣偵測器與正交可調延遲電路，重複利用延遲量測電路，提供了一個與同步時脈
訊號相差了90 度相位的正交相位輸出，建立一組I/Q 通道。本電路將可適用於低電壓
時脈同步與資料傳送的應用，如生醫訊號感測系統。因其採全數位低電壓操作進行設計，
並將可適用於單晶片系統設計。
本論文之同步複製延遲電路使用TSMC 90 nm 1P9M CMOS 製程實現晶片，電路
操作電壓為0.5 V，其操作頻率範圍可從220 MHz 到570 MHz，同步時脈間之相位誤
差≦100.5 ps，正交同步時脈間之相位誤差≦144.4 ps。在操作頻率為570 MHz 時，功
率消耗為1.95 mW。而內部時脈輸出訊號之最大峰對峰值時間抖動量為31.78 ps (1.81
%)，方均根抖動量為3.99 ps，正交相位輸出訊號之最大峰對峰值時間抖動量為34.67 ps
(1.97 %)，方均根抖動量為4.48 ps。整體晶片面積為517 × 594 um2，核心電路的面
積為188 × 171 um2。

關鍵字

低電壓 ； 多相位輸出 ； 同步複製延遲電路 ； 時脈同步電路

並列摘要

Abstract
A low supply voltage synchronous mirror delay circuit with quadrature phase
clock output is proposed. The coarse tune operation of this clock synchronous circuit
is accomplished in five cycles, and then the fine tune operation is also accomplished
in following eight cycles. Therefore, the clock signal is synchronized by the two step
operations. The fine tune operation not only can reduce the static clock phase error
but also can dynamic calibrate the synchronized clock by using a ring circuit. The two
step edge detector and the quadrature variable delay line are use in the proposed
SMD to generate a quadrature phase output, which is lagging from the synchronous
internal clock with a 90° phase shift. The quadrature phase output is useful for low
voltage clock synchronous and data transmission application, like biomedical signal
sensor network. The proposed SMD is using the all-digital circuit design and operating
at low supply voltage, thus it is suitable for system-on-chip (SoC) systems application.
The experimental chip was fabricated by TSMC 90 nm 1P9M CMOS process.
The chip is operating at 0.5 V supply voltage. The static phase error between
synchronous clocks is less than 100.5 ps, furthermore the static phase error between
quadrature clocks is less than 144.4 ps. The measurement results show that the
operation range is from 220 MHz to 570 MHz, and the power consumption is 1.95 mW
at 570 MHz. The peak-to-peak jitter and RMS jitter of internal clock are 31.78 ps and
3.99 ps at 570 MHz, respectively. The peak-to-peak jitter and RMS jitter of quadrature
internal clock are 34.67 ps and 4.48 ps at 570 MHz, respectively. The whole chip area
is 517 × 594 um2, and the core area is 188 × 171 um2
.

並列關鍵字

multiphase ； clock synchronous circuit ； synchronous mirror delay ； low voltage

參考文獻

Locking Arbitrary Duty Cycle Clock Synchronization Circuit,” IEEE Trans. Very

[2] T. Sakurai, “Low Power Digital Circuit Design,” IEEE European Solid-State

Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T.

250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay,” IEEE J. Solid-State

CMOS Digital Clock Generator Based on An Interleaved Synchronous Mirror