雙頻帶射頻接收機前端電路設計

2.4/5.7GHz DUALBAND RF RECEIVER FRONT-END CIRCUIT DESIGN

羅仕孟(Shi-meng LUO)

指導教授 ： 詹耀福

大同大學/電機資訊學院/電機工程學系所/碩士(2005年)

摘要

在本論文中，我們設計一雙頻帶(2.4GHz及5.7GHz)的射頻接收機前端電路其電路包含了雙頻低雜訊放大器、混波器和壓控振盪器，使用台積電 0.18μm CMOS製程參數來設計電路，且使用安捷倫EEsoft EDA-ADS模擬。由於雙頻接收機需同時接收兩個頻帶的訊號，因此我們使用雙頻同步接收之低雜訊放大器。此外所設計之低雜訊放大器為單端的架構，因此需要一主動的balun以連接到主動雙平衡的混波器。壓控振盪器是設計操作在4.2GHz，透過混波器可將2.4GHz及5.7GHz信號分別降到1.8GHz及1.5GHz之中頻。就2.4GHz而言，此接收機提供了32.11dB的增益及3.26dB的雜訊指數，功率消耗為55.36mW。在5.7GHz時，提供了15.92dB的增益及7.64dB的雜訊指數，功率消耗為55.36mW。整體的相位雜訊為115.9dBc/Hz@1MHz。

關鍵字

低雜訊放大器 ； 雙頻帶 ； 射頻接收機

並列摘要

This thesis describes the design and implementation of the front-end circuit of a 2.4/5.7 GHz dualband receiver. The circuit blocks include a concurrent dualband LNA, a mixer and a VCO using TSMC 0.18μm 1P6M CMOS process. Because the dualband receiver receives the two desire signals simultenously, a concurrent dualband LNA is adopted. The proposed LNA is single-ended, and it needs an active balun to connect the LNA to active double-balanced mixer. The designed VCO oscilating at 4.2 GHz, makes the RF signals for 2.4GHz and 5.7GHz downconvert to the first IF of 1.8GHz and 1.5GHz, respectively. For the 2.4GHz band, the front-end circuit for the receiver provides overall gain of 32.11dB and noise figure of 3.26dB, and the total power dissipation is 55.36mW. For the 5.7GHz band, the overall gain of the receiver is 15.92dB, and the overall noise figure is 7.64dB, and the total power dissipation is 55.63mW. The phase noise of dualband receiver is 115.9dBc/Hz@1MHz.

並列關鍵字

Dual-band ； LNA ； RF receiver

參考文獻

[1] C. P. Yue, C. Ryu, J. Lau, T. H. Lee, and S. S. Wong, “A physical model for planar spiral inductors on silicon,” in Proc. Int. Electron Devices Meeting, 8-11, pp. 155-158, Dec. 1996.

[4] H. Fouad, K. Sharaf, E. El-Diwany, and H. El-Hennawy, “An RF CMOS cascade LNA with current reuse and inductive source degeneration,” in Proc. of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, 2001, Vol. 2, pp. 824-828, 14-17 Aug. 2001.

[5] A.H. Mostafa, M.N. El-Gamal, and R.A. Rafla, “A Sub-1-V 4-GHz CMOS VCO and a a 12.5-GHz oscillator for low-voltage and high-frequency applications,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Proc., vol 48,pp. 919 -926, Oct. 2001.

[7] P. Andreani, A. Bonfanti, L. Romano, and C. Samori, “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” IEEE J. Solid-State Circuits, Vol. 37, pp. 1737 -1747, Dec. 2002.

[2] B. Razavi, RF Microelectronics. Prentice Hall PTR, 1997.