系統單晶片效能與功率評估平台之建置

隨著半導體技術的日益進步，我們可以設計整個系統在一顆晶片上。系統單晶片可以減少整個系統的花費、增加效能、減少功率消耗並且減少晶片的面積。但是也增加了設計整個系統晶片的複雜度。為了要在設計晶片前探究系統單晶片平台，我們設計了一套"系統晶片效能與功率評估平台"。一個系統單晶片平台包括一個微處理器、記憶體結構、連結匯流排、週邊和多個矽智財(IP)。對於一個系統單晶片的設計者而言，最大的挑戰就是在設計流程之前量測效能與功率。這篇論文提出一個系統級時脈精確的效能與功率評估經由高效率的軟硬體共同模擬。

關鍵字

系統單晶片；效能；功率；複雜度；微處理器；記憶體結構；矽智財；系統級；軟硬體共同模擬

並列摘要

With the improvement of semiconductor technology, it is now possible that we could construct the whole system on a single chip (SoC). SoC can reduce overall system cost, increase performance, lower power consumption, and reduce chip size. But it also increases the sys-tem design complexity. To facilitate early design space exploration for platform SoC, we are currently developing a system-level performance/power evaluation framework. A platform- based SoC contains a microprocessor, memory hierarchy, interconnected buses, peripherals,and a set of IP cores. For a platform SoC designer, it is challenging to determine platform components in view of performance and power at the early stage of the design °ow. The proposed system-level simulation framework provides cycle-accurate performance and power evaluation at the system-level through e±cient hardware-software co-simulation.

並列關鍵字

system on a single chip (SoC) ； performance ； power ； complexity ； microprocessor ； memory hierarchy ； IP cores ； system-level ； hardware-software co-simulation

參考文獻

co-simulation and emulation of multi-processor soc designs," IEEE Computer, vol. 36,

and Keith Ahluwalia, Amba ahb cycle level interface (ahb cli) speci‾cation ah-

Academic Publishers, 2002.

proach," Kluwer Academic Press, 1997.

[6] L. Semeria and A. Ghosh, Methodology for hardware/software coveri‾cation in

國際替代計量

系統單晶片效能與功率評估平台之建置

全文下載

主題瀏覽