一個可動態調整通道的晶片網路架構設計

Design of a Network-on-Chip Architecture with Dynamically Reconfigurable Channels

羅士欣(Shih-Hsin Lo)

指導教授 ： 陳少傑

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.01615

摘要

本文提出一個使用雙向通道的晶片網路架構，它同時支援了不同服務品質的資料傳輸，使得晶片內部的傳輸效能有所改善。此雙向的晶片網路架構允許每一條通道能夠動態的自我調整傳送方向來提高晶片內硬體資源的利用率。對於每一個晶片網路的路由器而言，資料通訊的延遲時間，傳輸吞吐量，以及頻寬利用率都受到這個附加的通道靈活性影響而得到更好的效能。這篇論文呈現出一個創新的路由器架構設計以及一個控制雙向通道的機制。透過分析可以證明此架構的額外硬體成本是可忽略的。本文利用一個精準時脈週期的測試環境進行模擬，對於在假想的交通型態以及真實規格的傳輸情況下，此雙向通道的晶片網路相對於傳統的單向通道架構都能展現出可觀的效能優勢。

關鍵字

晶片網路 ； 路由器 ； 雙向通道 ； 虛擬通道 ； 服務質量

並列摘要

A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication while supporting prioritized traffics in the network. The BiNoC allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate at each on-chip router. In this Thesis, a novel on-chip router architecture supporting the self-configuring bidirectional channel mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulation runs on this BiNoC network under synthetic and real-world traffic patterns demonstrate consistent and significant performance advantage over a conventional mesh grid NoC architecture equipped with hard-wired unidirectional channels.

並列關鍵字

Network-on-Chip ； Router ； Bidirectional Channel ； Virtual Channel ； Quality-of-Service

參考文獻

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