使用CMOS製程內含線性時脈資料回復電路之56-Gbps PAM4接收機

A 56-Gbps PAM4 Receiver with Linear CDR in CMOS Technology

儲翔雲(Hsiang-Yun Chu)

指導教授 ： 李致毅

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10880

摘要

本論文中實現一帶有時脈資料回復功能的四進位脈衝振幅調變接收器。其中的時脈資料回復架構為全速率線性時脈資料回復，以往多半應用於二進位資料流如反相不歸零制。本實驗證明了相同架構亦可適用於四進位脈衝振幅調變。這意味著所有現存內含這種時脈資料回復架構的接收器，可以在簡單修改後將傳輸輸率提升為兩倍。本接收器由65奈米互補式金氧半製程製作，可以接收經由15公厘rogers電路板通道的56 Gb/s訊號。回復時脈的方均根抖動小於400 fs，而誤碼率則小於10^-12。

關鍵字

四進位脈衝振幅調變 ； 時脈資料回復 ； 全速率線性時脈資料回復

並列摘要

In this thesis, a 4-ary pulse-amplitude modulation (PAM4) receiver with clock and data recovery (CDR) has been implemented. The CDR in the receiver is a full-rate linear CDR which often be applied in two levels signal receiver like non-return-to-zero (NRZ). This work demonstrates the design can be used for PAM4 signal, too. This means every existed transceiver based on the CDR can reach double data rate with simple modification. Fabricated in 65-nm CMOS technology, the receiver can receive 56 Gb/s PAM4 signal transmitted by 15 mm rogers channel. The recovery clock rms jitter is less than 400 fs and the bit error rate (BER) of recovery data is under 10^-12.

並列關鍵字

4-ary pulse-amplitude modulation (PAM4) ； clock and data recovery (CDR) ； full-rate linear CDR

參考文獻

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