摘要
在本文中，我們使用TSMC 0.35微米、2P/4M、混合模式、3.3/5V的製程資料以全客戶設計之方法設計一個乘法器。 依據文獻上之資料，有多種不同乘法器之架構，如 Baugh-Wooley 乘法器，陣列乘法器，序並行乘法器...等，此處我們採用最基本最直接的乘法運算過程去實現我們的乘法器，此乘法器由幾種基本邏輯閘構成，對每個邏輯閘我們調整其方位比，以得到適當之特性，並把它叫做基本細胞，在基本細胞被設計以後，我們用它來設計半加器、全加器和乘法器，所有電路均以HSPICE模擬驗證無誤，佈局、設計規則檢驗和電路佈局比對則以VIRTUOSO 和 CALIBRE 完成。
並列摘要
In this paper, we provide a method to implement an integrated circuit of multiplier, a full-custom design, with TSMC 0.35 um, 2P/4M, mixed-mode, 3.3/5V-process technology. Different from the design methods of others kinds of multipliers (such as the Baugh-Wooley multiplier, the array multipler, and the serial-parallel multiplier), we use the basic multiplication to design our circuit, which is composed by several basic logic gates. For each gate, which is called the basic cell, we adjust its aspect ratio to derive proper characteristics. Then, the half-adder, full-adder, and the multiplier are designed based on those basic cells. Finally, all the circuits and layouts are simulated and verified by the HSPICE, VIRTUOSO and CALIBRE.
延伸閱讀
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