應用於5G通訊之相移器與功率偵測晶片

Phase Shifters and Power Detectors for 5G Communication

葉鋆宣(Yun-Hsuan Yeh)

指導教授 ： 盧信嘉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201603004

摘要

本論文主要研究領域為開關式相移器與功率偵測電路，由於高速通訊蓬勃發展，除了傳統的語音傳輸，更進一步發展至圖片與影片之傳輸。因此通信訊號的頻率日益提升，以應付高速通訊之需求。現今以5G通訊系統為通信發展之主流，操作頻率為38 GHz，因此本論文所提之電路即以此頻段作為發展之重點。
本論文前半段則針對各式相移器與功率偵測電路架構進行介紹，並就其原理加以分析，考量使用的用途，選定開關式相移器做為本論文所提之架構。二版之相移器晶片則針對第一版電路由於電晶體模型不準造成之相位誤差部分加以改良，提出一整合開關式相移器與反射式相移器之整合電路，以連續可調之反射式相移器修正因製程影響所造成之相位誤差，使相位誤差可小於 ，振幅誤差則可小於1.5 dB。而於功率偵測電路部分，首先選定之架構為交叉耦合式整流電路，由於此電路架構具有較高之輸出電壓，其輸出電壓範圍為1 mV至700 mV，有利於簡化功率偵測電路之設計，並與天線整合為同一晶片，可以減少電路間轉接損失並降低製作成本。其最低可偵測功率為 dBm，直流功耗為29 mW。而二版之功率偵測電路，則為了提升原先電路之偵測功率範圍，故採用自混式整流電路，並輔以低雜訊放大器與運算放大器，使可偵測之最小功率可達 dBm，輸出電壓範圍為125 mV至1.6 V，直流功耗為31.5 mW，使此功率偵測電路能具有更廣泛的應用度。
而本論文後半段則是分別對於所提之四種電路進行設計，針對其架構進行更進一步的分析，同時並採用ADS軟體進行電路模擬，被動元件之電磁模擬則使用Sonnet軟體。本論文之所提之四個電路分別使用台積電之40 nm、65 nm、90 nm與180 nm CMOS製程實現，而所提之開關式相移器與具有天線之功率偵測電路已於國立台灣大學電機二館進行高頻量測驗證，其量測結果可佐證本論文之模擬結果，並可證實本論文所提之電路架構確實可實現相移器與功率偵測電路。

關鍵字

5G通訊 ； 開關式相移器 ； 反射式相移器 ； 功率偵測電路 ； 交叉耦合式整流器 ； 自混式整流器

並列摘要

This thesis studies the switch type phase shifters and power detectors. To satisfy the demand of high-speed mobile wireless communications, the 5G mobile communication is under developing and the operating frequency is 38 GHz. Therefore, this thesis chooses this band as the operating frequency of proposed circuits.
This thesis first reviews the architectures of different types of phase shifters and power detectors, and also analyzes the operation principles of these circuits. Considering the application, this thesis chooses switch type phase shifter as main architecture. To reduce the phase error caused by the inaccuracy of transistor model, this thesis proposes a phase shifter combining the switch type and reflection type phase shifter. With continuous tuning voltage, it can correct the phase error caused by process variation. It can achieve the phase imbalance of less than and the amplitude imbalance of less than 1.5 dB.
On the other hand, cross-coupled pair rectifier has been chosen for the first architecture of power detector. The circuit has the advantage of high output voltage ranging from 1 mV to 700 mV without additional op-amp, so it can simplify the circuit design. Furthermore, the cross-coupled pair rectifier is integrated with an on-chip antenna. It can not only reduce the transfer loss between rectifier and antenna but also reduce production costs. The minimum detectable power of this circuit is dBm and the DC power consumption is 29 mW. In order to increase the detectable power range, the second version of power detector applies self-mixing rectifier as detector circuit, and adds the low noise amplifier and operation amplifier. It achieves the minimum detectable power at dBm and the output voltage range at 125 mV to 1.6 V. The total DC power consumption is 31.5 mW.
In this thesis, the proposed circuits have been designed by Keysight ADS and Sonnet for the circuit and EM simulation. The circuits developed in TSMC 40 nm, 65 nm, 90 nm and 180 nm CMOS technology respectively. The switch type phase shifter and power detector with on-chip antenna have been measured in National Taiwan University E.E. Building No.2 with high frequency measurement instrument. The measurement results prove the properties of proposed circuits.

並列關鍵字

5G communication ； switch type phase shifter ； reflection type phase shifter ； power detector ； cross-coupled pair rectifier ； self-mixing rectifier

參考文獻

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