透過您的圖書館登入
IP:18.118.0.236
  • 學位論文

具連續波固態綠光雷射側向結晶通道之n型多晶矽薄膜電晶體其電氣特性與可靠度研究

The Electrical Characteristics and Reliability Considerations of N-channel Poly-Silicon Thin-Film Transistor with Continuous-Wave Solid-State Green Laser Lateral Crystallization Channel

指導教授 : 黃恆盛 王木俊

摘要


一般之平面顯示器,皆期盼螢幕畫面,無漏光、無殘影、高解析度、高畫質等鮮明畫質。坊間之平面顯示器產品,大都使用非晶矽薄膜電晶體作為下基板之電路控制開關,由於電子遷移率過低 (~ 1 cm2/V-sec) ,導致源/汲極之間的電流較低。因此,電晶體之開關速度也相對地較慢,使得大尺寸螢幕之開發,遇到很大的瓶頸,無法使一個大畫面其反應時間小於8 msec.。業界著眼於此,因而有低溫多晶矽(low-temperature poly-silicon, LTPS)之開發,其電子遷移率可拉升至~ 100 cm2/V-sec或以上。 本論文所研究之連續式綠光雷射退火結晶,加上綠光雷射活化,有效地提升薄膜電晶體通道電子遷移率,可拉升至~ 530 cm2/V-sec,使此薄膜電晶體的可應用範圍更往前提昇,對於電路製作在玻璃基板(Chip-on-Glass, CoG)的可行性又大大地往前邁進。 在元件電特性與可靠性方面,將著重於閘極氧化層品質探討與元件熱載子的劣化機制,與在不同溫度與電性頻率下之電子或電洞行為模式之探討,以確保在製程後,元件之可靠性壽命能符合業界要求。

並列摘要


The requests of flat-panel display performance expectantly contain no optical leak, no residual image, high resolution, great and colorful display quality, etc. In present display industry, most of display products adopt the amorphous-silicon thin-film transistors (TFTs) on the bottom glass substrate to control the signal circuit. Because of the low electron mobility (~ 1 cm2/V-sec), the source/drain current is also low and the transistor switching speed relatively is slow. This electrical characteristic, which can not provide the response time < 8 msec, will constrain the development of big-size display products. Due to this concern, the low-temperature poly-silicon (LTPS) technology was developed. The electron mobility could be promoted to ~ 100 cm2/V-sec or behind. In this study, the LPTS TFTs with high electron mobility, ~ 530 cm2/V-sec, were fabricated by continuous-wave green-laser-crystallization (CLC) and the green-laser activation technology. This transistor can be promisingly applied to many display fields. This device also provides the feasibility of chip-on-glass (CoG) circuits. In this work, some stress metrologies were developed to probe the device integrity in latent defects correlated to the reliability and the lifetime issue. The stress conditions chiefly focus on electrical field and temperature effect to understand the degradation mechanisms among gate oxide integrity, gate oxide/channel interface, channel quality and channel/bottom oxide interface contribution. The parameter extraction methods were also developed to interpret the device quality and the degradation mechanisms, especially in the behaviors of conductive electrons and holes. Through these efforts, the device quality and the device lifetime can be made sure to satisfy the industrial needs.

參考文獻


[1.1] S. Zhang, C. Zhu, Johnny K. O. Sin, J. N. Li, and Philip K. T. Mok, “Ultra-Thin Elevated Channel Poly-Si TFT Technology for Fully-Integrated AMLCD System on Glass,” IEEE Trans. Elect. Devices, 54, 569, 2000.
[1.2] H. Baek, M. Lee, J. H. Lee, H. S. Pae, C. J. Lee, J. T. Kim, C. S. Choi, H. K. Kim, T. J. Kim, and H. K. Chung, IEEE J. Solid-State Circ., 41, (2006) 2974
[1.3] P. Barquinha, A. M. Vilà, G. Gonçalves, L. Pereira, R. Martins, J. R. Morante, and E. Fortunato, IEEE Trans. Elect. Dev., 55, (2008) 954
[1.4] C. W. Lin, M. Z. Yang, C. C. Yeh, L. J. Cheng, T. Y. Huang, H. C. Cheng, H. C. Lin, T. S. Chao, C. Y. Chang, IEEE IEDM, (1999) 305
[1.5] S. Zhang, C. Zhu, Johnny K. O. Sin, J. N. Li, and Philip K. T. Mok, “Ultra-Thin Elevated Channel Poly-Si TFT Technology for Fully-Integrated AMLCD System on Glass,” IEEE Trans. Elect. Devices, 54, 569, 2000.

延伸閱讀