可供類比腓特比解碼器使用之決策裝置晶片設計

IC Design of a Decision Device for Analog Viterbi Decoder

呂銘峻(Ming-Jiun Liu)

指導教授 ： 李文達

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2005年)

摘要

傳統的無線通訊硬體製作步驟，在訊號進入到解調變與通道解碼之前，都必須使用一顆高解析度與高速度的類比/數位的轉換器。因此本論文提出一種新型類比式電路架構，可在不使用類比/數位的轉換器地情況下，做數位解調變系統之功能。
在方法上，我們針對解調變部分採QAM處理方式完成類比式決策裝置電路架構，同時配合後端處理，我們也完成一類比式腓特比解碼器前端處理電路架構設計。最後我們採用UMC 0.18-μm CMOS 1P6M的製程技術，完成一顆類比式決策裝置晶片及一顆類比式腓特比解碼前端晶片。在決策裝置晶片中共使用了494顆電晶體所建構而成，晶片含I/O-PAD的面積為0.544mm2，電路最大的操作頻率將可達到100Mb/s，且消耗功率為17.46mW。在類比式腓特比解碼前端處理晶片中，則使用了164顆電晶體，晶片面積為0.286 mm2，電路最大的操作頻率可達到100MHz，且消耗功率為22.2mW。上述晶片設計具有低功率、小面積、低成本優點，容易與前端射頻接收器結合，未來可供新型SOC 通訊系統之應用。

關鍵字

無線通訊 ； 類比/數位轉換器 ； 類比決策裝置 ； 類比腓特比解碼器

並列摘要

In transitional implementation of wireless communication, it is essential to use a high-speed and high-resolution A/D converter when the receiver signal gets into the digital demodulator and channel decoder.
In this paper, we present a new structure that can process the demodulation without A/D converter.
In our method, we have designed an analog decision device using QAM demodulator. Meanwhile, to verify our method, we have also finished a front-end analog Viterbi decoder circuit. Finally, we have designed one analog decision chip and one front-end analog Viterbi decoder chip with UMC 0.18-μm 1P6M CMOS technology. In the decision device chip, it contains 494 transistors, operates to 100Mb/s using a single 3.3-V power supply and consumes 17.46mW. The chip area of the analog decision is about 0.544mm2 . The front-end analog Viterbi decoder chip contains 164 transistors, operates to 100MHz using a single 3.3-V power supply and consumes 22.2mW. The chip area of the analog decision is about 0.286mm2. These chips have the advantages of low-power, small-area, low-cost and are easy to be combined with the RF Front-End Receiver. The new architecture can provide an efficient design for future SOC communications.

並列關鍵字

Wireless Communication ； A/D Converter ； Analog Decision Device ； Analog Viterbi Decoder

參考文獻

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