鎖相式頻率合成器之設計分析

Design and Analysis of Phase-Locked-Loop-Based Frequency Synthesizer

陳燕虹(Yen-hung Chen)

指導教授 ： 張原豪

朝陽科技大學/資訊學院/資訊工程系/碩士(2009年)

摘要

摘要

本論文我們設計一個以鎖相迴路做為基礎的頻率合成器。鎖相迴路為廣泛應用於電子與通訊電路中之重要元件，它的用途為解決積體電路在高速及高整合度環境下的時脈誤差及頻率合成的問題。頻率合成器的應用廣泛，例如：電視機的選台器、無線網路卡等只要關乎頻率的鎖定都有它的存在，論文中的目的在於介紹頻率合成器的理論分析和實際設計一個頻率合成器的設計過程。
我們以台灣積體電路TSMC0.35um 2P4M製程來實現此頻率合成器，在工作電壓為3.3V，整個頻率合成器銷耗功率為40mW。本壓控振盪器振盪的頻率輸出範圍可從2.14GHz至2.75GHz，以防止當製程環境變動影響時，壓控振盪器無法合成預期高頻信號輸出；經觀察模擬結果，頻率合成器在各種不同邊緣模型(Corner Model)環境變動下仍可穩定輸出，當偏移頻率1MHz時，所量測之相位雜訊為-104dBc/Hz。

關鍵字

鎖相迴路 ； 頻率合成器

並列摘要

ABSTRACT
In this thesis we design a frequency synthesizer based on phase-locked- loop. The PLLs are important components widely used in the electronic and communication circuits. They are used to solve the clock skew and frequency synthesis problems of ICs in a fast operation speed and highly integrated environment. The application of the frequency synthesizer is extensive, for example: Television select platform device, so long as wireless network card ,etc. concern locking of frequency have existence of it, the purpose of this thesis lies in recommending the theory of the frequency synthesizer to analysis and the actual design process of a frequency synthesizer.
The TSMC 0.35 um BiCMOS Mixed Signal SiGe 2P4M process is used to implement the frequency synthesizer； its consumption power of the frequency synthesizer is 40mW with the 3.3V power supply. A wide range of ring VCO operation frequency, 1.1GHz-2.8GHz, is designed to ensure that the VCO still can generate the desired frequency even when the process conditions vary. Simulation results demonstrate that the synthesizer obtains a steady output signal under dierent corner models. The phase noise is obtained to be -106dBc/Hz.

並列關鍵字

Frequency Synthesizer ； Phase-Locked-Loop

參考文獻

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