In this thesis, we have developed a novel double patterning technique utilizing an i-line stepper for the formation of sub-100nm gate patterns and implemented this technique to the fabrication of devices. This technique consists of 2-step lithography and following etch process to form the gate patterns. Reward for the complicated process steps is the shrinkage of resulted patterns beyond the resolution limit of the conventional i-line lithographic method (~0.3m), since this technique doesn’t suffer the diffraction effect encountered in conventional process. Resolution capability of this technique has been confirmed to improve at least to 80nm in this thesis. Several types of devices with asymmetrical source/drain structure, such as tunneling field-effect transistors (TFETs) and n-MOSFETs with asymmetric extensions, were fabricated with this technique and characterized in this thesis.