採用切換式運算放大器共享技術之一伏特十位元10MSample/s管線式類比數位轉換器

本篇論文主要描述一個低功率、10位元、操作頻率在10MHz而工作電壓在1V的管流式類比數位轉換器之設計，並提出利用切換式運算放大器共享技術來減少轉換器元件數量。有別於一般的低功率低電壓電路，本架構不需要過多的運算放大器，單純利用開關切換以降低功率以及達成運算放大器共用。本轉換器採用標準0.18um 1P6M CMOS製程，並透過Hspice模擬電路架構。本轉換器操作在10MHz的取樣頻率，工作電壓為1V，輸入頻率為530kHz下SNDR為51.66dB，其總功率消耗為18mW。

關鍵字

放大器共享；類比數位轉換器；管線式類比數位轉換器；切換式放大器技術

並列摘要

In this thesis, a 10-bit 10-MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed and verified by Hspice simulation with TSMC 0.18-µm 1P6M CMOS process models. In order to operation at 1V, the switched-opamp technique is employed in the pipelined ADC. In order to saving the power consumption and chip area, the analog-to-digital converter merges two output stages using an opamp-sharing technique. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 51.66 dB with sampling frequency of 10 MHz at input frequency of 530 kHz. Power consumption of this ADC is 18mW with 1V power supply.

並列關鍵字

POAMP-SHARING ； ADC ； PIPELINED ADC ； SWITCHED OPAMP

參考文獻

[1] R. Lotfi, O. Shoaei, “A Low-Voltage Low-Power Fast-Settling Operational Amplifier for Use In High-Speed High-Resolution Pipelined A/D Converters,” in Proc. IEEE International Symposium on Circuits and Systems, ISCAS 2002, Vol. 2, pp. 416-419, May 2002.

[2] J. Steensgaard, “Bootstrapped Low-Voltage Analog Switches,” IEEE, International Symposium on Circuits and Systems, Vol. 2, pp. 29 - 32, June 1999.

[3] W. C. Song, H. W. Choi, S. U. Kwak, and B. S. Song, “A 10-b, 20-Msampl/s Low-Power COMS ADC,” IEEE J. Solid-State Circuits, Vol. 30, No.5, pp. 514 – 521, May 1995.

[4] S. H. Lewis and P. R. Gray, “A Pipelined 5-Msamples/s 9-bit Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, Vol. SC-22, pp. 954-961, Dec. 1987.

[6] S. Lewis, et al, “10-b 20Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, Vol. 27, pp. 351-358, Mar. 1992.

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採用切換式運算放大器共享技術之一伏特十位元10MSample/s管線式類比數位轉換器

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