Testable Path Delay Fault Cover for Sequential Circuits

We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently affect the performance of the circuit, or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two- or multi-level netlists. The outcome of applying our methodology is a smaller fault set and possibly a smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or do not have to be examined for delay defects.

並列關鍵字

delay testing ； path delay faults ； timing defects ； sequential circuits ； untestable path delay faults

被引用紀錄

吳逸翔（2015）。時域分析之連續漸進式類比數位轉換器與每秒取樣10億次之6位元導管式類比數位轉換器〔碩士論文，國立清華大學〕。華藝線上圖書館。https://doi.org/10.6843/NTHU.2015.00403

國際替代計量

Testable Path Delay Fault Cover for Sequential Circuits

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