背景校正供應電壓雜訊之數位鎖相迴路與注入鎖定時脈倍頻器

Digital Phase-Locked Loop With Background Supply Noise Calibration and Injection-Locked Clock Multiplier

田哲瑋(Che-Wei Tien)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201701461

摘要

這篇論文的主題主要分為兩個部分，第一部分實現了一個具有背景校正供應電壓敏感度之數位鎖相迴路。利用一個全數位的校正方法加上頻率相減器去抑制供應電壓敏感度。在振盪器的供應電壓注入峰對峰值為50mV，頻率為100kHz的弦波雜訊時，量測到的峰對峰值抖動量從原本的41.48ps降低至23.15ps。量測到的方均根抖動量從原本的7.26ps 降低到3.47ps。在未注入供應電壓雜訊時，量測到的峰對峰值和方均根抖動量分別為 19.21ps 和2.71ps。此全數位鎖相迴路的面積與功耗分別為0.006mm2以及9.34mW。
第二部分實現了一個注入鎖定時脈倍頻器。透過使用延遲時間偵測器的頻率校正器，達到校正因為製程、電壓以及溫度變異造成的頻率誤差。參考突波以及時間抖動可以被顯著地降低。當注入鎖定之後，量測到的參考突波為-61.28dBc，積分範圍從10kHz到100MHz的方均根抖動量為479fs。此注入鎖定時脈倍頻器的面積與功耗分別為0.012mm2以及2.55mW。

關鍵字

鎖相迴路 ； 供應電壓雜訊 ； 注入鎖定 ； 時脈倍頻器

並列摘要

This thesis consists of two parts. The first part implements a digital phase-locked loop (DPLL) with background supply voltage sensitivity calibration. A digital supply voltage sensitivity controller with a frequency subtractor is used to suppress the supply voltage sensitivity. With a 50mVPP, 100kHz sinusoidal supply noise tone, the calibration scheme reduces the peak-to-peak jitter from 41.48ps to 23.15ps and the rms jitter is reduced from 7.26ps to 3.47 ps. The measured peak-to-peak jitter and rms jitter without supply noise are 19.21ps and 2.71ps. Its active area is 0.006mm2 and the power consumption is 9.34mW.
The second part implements an injection-locked clock multiplier (ILCM). The ILCM is presented with a frequency calibrator (FC) using a delay time detector to calibrate the frequency error due to the process, voltage, and temperature (PVT) variations. The reference spur and timing jitter due to the PVT variations can be significantly reduced. When injection locked, the measured reference spur is -61.28dBc and the rms jitter integrated from 10kHz to 100MHz is 479fs. Its active area is 0.012mm2 and the power consumption is 2.55mW.

並列關鍵字

phase-locked loop ； supply noise ； injection-locked ； clock multiplier

參考文獻

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