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Inductorless CMOS Receiver Front-End Circuits for 10-Gb/s Optical Communications

並列摘要


In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dBΩand a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplifier employs interleaving active feedback to achieve a differential voltage gain of 44.5 dB and a bandwidth of 10.3 GHz while consuming 226 mW. Both circuits are realized in 0.18-μm CMOS technology with a 1.8-V supply.

被引用紀錄


Huang, C. C. (2013). LED照明的電源IC設計和實現 [doctoral dissertation, Tamkang University]. Airiti Library. https://doi.org/10.6846/TKU.2013.00662
黃柏暵(2012)。線性穩壓器與切換式轉換器於可攜式應用之研製〔博士論文,國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2012.00329
Tseng, C. J. (2016). 高速低功率之管線式類比數位轉換器 [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU201610501
林昇緯(2013)。一個單通道六位元一次兩位元轉換每秒十二億次取樣的連續漸近式類比數位轉換器〔碩士論文,國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2013.00685
Lin, W. Y. (2009). 一個十位元高速低功率之循序趨近式類比數位轉換器 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2009.02221

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