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  • 學位論文

矽導通孔製程工程特性之研究

Engineering Analysis of Through-Silicon Via (TSV) Process

指導教授 : 楊宏智
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摘要


因應市場對電子產品輕薄之需求,半導體產業不斷地快速發展。為解決目前二維製程微縮上所遇到的困難,讓摩爾定律(Moore’s Law)能夠延續,應用矽導通孔(TSV)連接之三維積體電路(3D IC)構裝技術成為產業積極發展的重要技術-其關鍵便在於矽導通孔製程。其中,若一開始的鑽孔製程品質不良,便會對後續製程品質造成影響,進而導致整體成本提升。是故本論文提出在矽深蝕刻完成鑽孔後,進行金屬化製程前,導入業界成熟的濕蝕刻製程,調整製程參數,以提升矽導通孔品質,並透過電子顯微鏡實際觀察與量測其電性進行濕蝕刻效果之驗證。 根據實驗結果,鑽孔後若利用濕蝕刻,則能清除矽深蝕刻造成的波浪狀側壁,成功得到平滑側壁,並在後續物理氣相沉積製程中,使金屬層覆蓋率獲得顯著提升。對於孔徑80um經過濕蝕刻處理後的孔洞,其填銅比例也相對較高。而在電性方面,經過濕蝕刻處理的矽導通孔除表現較佳,量測結果之電阻值與漏電流亦相對較低。總結,本研究開發出業界可用的濕蝕刻製程,有效提升孔洞品質,並確認矽導通孔電性能有所提升。

並列摘要


In order to satisfy market demand on lighter and smaller electronic products, semiconductor industry has developed rapidly. To solve challenges on shrinkage process and to make the Moore’s law continue, three-dimensional integrated circuit (3D IC) technology with through-silicon via (TSV) becomes the major technology and so urgent to be carried out. The TSV process is critical for 3D IC technology. If quality of drilling process is not good enough, the following process of TSV would be affected and whole manufacturing cost would increase. The thesis is commenced with a new process to improve via quality with wet chemical etching (WCE) by adjusting parameters. The etching process would be performed after drilling process and before the metallization process. The result would be examined by scanning electron microscope, and the electrical characteristic would be tested to justify via quality improved by WCE. The experiment results reveal that WCE could clear sidewall scallop generated by deep reactive ion etching and successfully make sidewall smooth. After physical vapor deposition process, the metal coverage has been improved. For 80-um vias, copper filling ratio is higher for adoption of WCE. Moreover, electrical characteristics of TSVs like resistance and current leakage are improved. In summary, the thesis provides an acceptable process to improve TSV quality which also be confirmed .

參考文獻


[1] J.H. Lau., "Overview and outlook of through-silicon via (TSV) and 3D integrations, "Microelectronics International, Vol. 28 Iss: 2, pp.8 – 22. (2011).
[2] T. K. Ku., "3D TSV Stacking IC Technologies, Challenges & Opportunities ", AMD Technique Forum. (2011).
[3] Sunohara, M.; Tokunaga, T.; Kurihara, Takashi; Higashi, M., "Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring," Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, vol., no., pp.847,852. (2008).
[4] Y. C. Hsin. ; C. C. Chen. ; J. Lau. , "Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers," Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, vol., no., pp.1130,1135. (2011).
[5] J.H. Lau., "Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration," Advanced Packaging Materials (APM), 2011 International Symposium on , vol., no., pp.462,488, 25-28. (2011).

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