在兩層板設計架構上的電源完整性與信號完整性之個案研究

Case Studies of Power Integrity and Signal Integrity on Two-Layer PCB Design

張榮展(Jung-Chan Chang)

指導教授 ： 林丁丙

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2009年)

https://doi.org/10.6841/NTUT.2009.00415

摘要

本論文針對複雜的系統電路在兩層板上運作時，所產生電源完整性問題及訊號完整性問題作研究探討與分析，並提出改善的方向。各種高效能產品為了讓各類不同性質的電路（例如：類比電路、高速數位電路、射頻電路）能共同運作在同一印刷電路板(Print Circuit Board, PCB)上，大部分皆採用有完整參考平面的多層板架構(四層板以上)來設計，以降低訊號與訊號間彼此的電磁場干擾，例如耦合效應；也可降低訊號在電源上的干擾，例如同步交換雜訊（Simultaneous Switching Noise, SSN）；甚至減少整體系統電路所產生電磁干擾（Electromagnetic Interference, EMI）。

在現今商品價格競爭激烈時代裡，消費者期望產品不只是要高效多工，且價格也要經濟實惠。因此，高效能複雜且多功的系統電路採用兩層板設計，已經成為現今產品研發的主要課題。本篇論文以整合型數位電視（Integrated Digital Television, IDTV）產品為研究主題平臺，成功讓此系統電路穩定運作於兩層板的架構上，並以四大個案作為研究探討：1.改善差動訊號在互連裝置上阻抗不匹配的方法；2.高阻抗面（High Impedance Surface, HIS）架構應用於兩層板上的TV調諧器佈局；3. DDR SDRAM傳輸介面在兩層板系統上的訊號完整性分析與改善；4.在兩層板系統上非理想電流回流路徑的訊號完整性問題分析與改善。透過這四項個案研究，提供業界一份混合電路在兩層板上的設計參考，也提供學界作為深入探討的方向。

關鍵字

兩層板 ； 電源完整性 ； 訊號完整性 ； 差動訊號 ； 阻抗匹配 ； 電流回流路徑

並列摘要

This thesis discusses and analyzes power integrity problem and signal integrity problem for complex system circuit working on two-layer print circuit board (PCB), and proposes the improvement method. Each kind of high efficiency product that in order to integrate heterogeneous circuits such as analog circuits, high-speed digital circuits and radio-frequency circuits to work on the identical PCB, the majority uses multi-layer PCB ( 4 layers or above ) which has ideal reference plane design, that can reduce the signals mutual electromagnetic field interference such as crosstalk, also can reduce the powers to be interfered by the signals such as simultaneous switching noise ( SSN ), and can decrease electromagnetic interference ( EMI ) from integral system circuit.

Nowadays are the times which compete with the cost. The consumers expect the products not only to be high performance and multi-functions but also to be inexpensive. Therefore the low cost system circuits that have high performance and multi-functions are designed by two-layer PCB, which already became major topic for products developing today. This thesis take integrated digital television (IDTV) as research subject platform, lets this system circuit stable operation successfully on two-layer PCB, and propose four kinds of major cases to discuss. 1. Impedance matching to interconnect differential pair for substrate and PCB layout. 2. HIS apply to TV tuner on two-layer PCB. 3. Signal integrity analyzes and improves for DDR SDRAM interface on two-layer PCB system. 4. Signal integrity analyzes and improves for non-ideal current return path on two-layer PCB system. Through these four kinds of case studies, not only proposes a design reference for hybrid circuits on two-layer PCB to industrial circles, but also proposes the direction of further study for academic circles.

並列關鍵字

Two-layer PCB ； power integrity ； signal integrity ； differential pair ； impedance matching ； current return path

參考文獻

[8] J. S. Pak, H. Kim, J. Lee, and J. Kim, ”Modeling and Measurement of Radiated Field Emission From a Power/Ground Plane Cavity Edge Excied by a Through-Hole Signal Via Based on a Balanced TLM and Via Coupling Model,” IEEE Transactions on Advanced Packaging, Vol. 30, no. 1, pp. 73-85, Feb. 2007.

[9] T. Kamgaing, and O. M. Ramahi, “Design and Modeling of High-Impedance Electromagnetic Surfaces for Switching Noise Suppression in Power Planes,” IEEE Transactions on Electromagnetic Compatibility, Vol. 47, no. 3, Aug. 2005.

[10] S. V. den Berghe, F. Olyslager, D. De Zutter, J. De Moerloose, and W. Temmerman, “Study of the ground bounce caused by power planes resonance,” IEEE Transactions on Electromagnetic Compatibility, Vol. 40, no. 2, pp. 111-119, -May. 1998.

[11] D. Sievenpiper, L. Zhang, R. F. J. Broas, N. G. Alexopolous, and E. Yablonovitch, “High-impedance electromagnetic suface with a forbidden frequency band,” IEEE Transactions on Microwave Theory and Techniques h, vol. 47, no. 11, pp. 2059-2074, Nov. 1999.

[12] R. Abhari and G. V. Eleftheriades, “Metallo-dielectric electromagnetic bandgap structures for suppression and isolation of the parallel-plate noise in high-speed circuits,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, no. 6, pp. 1629-1639, Jun. 2003.