類比電流模式之正交振幅解調變器晶片和(8,4)規則型低密度奇偶檢查碼之最小和解碼器晶片設計

Chips Design of Analog Current-Mode Quadrature Amplitude Modulation Demodulator and Min-Sum Decoder for (8,4) Regular Low-Density Parity-Check Codes

蘇皇祥(Huang-Shiang Su)

指導教授 ： 李文達

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2009年)

摘要

由於類比式解調變器和解碼器電路具有一定的解碼能力及具有低功率和低面積的優點，本論文提出以類比方式來完成一正交振幅調變和疊代解碼器之VLSI架構設計。在設計上我們分成兩個部份，第一為利用類比電路方式設計出新式解調變器，此設計主要由差動電路和電流鏡改善電路所組成。該解調變器架構可以有效將類比輸入訊號轉換成所屬星座圖位置，進而省略類比數位轉換器電路，並且可以直接將輸出訊號送至解碼端做解碼動作。第二為類比式低密度奇偶檢查碼解碼器的電路架構，它是以最小和演算法為設計基礎，其中電流鏡電路和校驗節點精確度問題是實現此架構重要的核心，我們利用調節疊接式電流鏡改善電路的高輸出阻抗與高精確度之優點，有效降低電流鏡之通道長度調變效應，同時改善解碼器訊息傳輸的精確度，提升整體電路之解碼效能。
最後我們將所提出的解調變器和高精確度低密度奇偶檢查碼解碼器，以TSMC 0.35μm 2P4M CMOS 製程技術設計驗證，此晶片分別包含106和1944顆電晶體，其工作電壓為3.3V，功率消耗分別約為402.9μW和12.04 mW，整個電路不包含I/O PAD的面積分別為0.14 × 0.13 mm^2 和0.52 × 0.2 mm^2。

關鍵字

類比式解調變器 ； 電流鏡 ； 正交振幅調變 ； 低密度奇偶檢查碼 ； 類比式疊代解碼器 ； 最小和演算法 ； 最小值贏者輸出電路

並列摘要

It was commonly believed that the analog demodulator and decoder have certainly error-correcting capacity and the advantages of low power consumption and lower silicon area. In this thesis, an analog quadrature amplitude modulation (QAM) demodulator and an analog iterative decoder of VLSI architecture design are proposed. First, we design a novel demodulator with analog circuits. The main design blocks are composed of differential pairs and current buffer circuits. The proposed demodulator architecture could transfer the analog input signals from the channel to the location of belonging constellation effectively and convey signals from the output of demodulator to decoder directly. Also, it can remove the analog to digital converter (ADC) device. The second design is the analog decoder architecture for low-density parity-check (LDPC) codes based on min-sum iterative algorithms. Current buffer circuits and check node accuracy issues are focal point for the architecture. We use the advantages of high output impedance and high accuracy to decrease the channel length modulation effect in cascode current buffers. Then, increase the transfer accuracy and decoding performance in the analog decoder.
Finally, a novel analog QAM demodulator and a high accuracy LDPC decoder have been implemented with 0.35μm 2P4M CMOS technology. These two chips include 106 and 1944 transistors respectively and operate in 3.3V power supply. The power consumption are 402.9μW and 12.04mW, the core area are 0.14 × 0.13 mm^2 and 0.52 × 0.2 mm^2 respectively.
The advantage of demodulator and decoder chips can achieve low power consumption, low cost and proper error correcting capacity that provides an efficient design for SOC integration in the communication receiver in the future.

並列關鍵字

analog demodulator ； current-mirror ； quadrature amplitude modulation (QAM) ； low-density parity-check (LDPC) codes ； analog iterative decoder ； min-sum algorithm ； winner-take-all

參考文獻

[37]Yu-Hsiang Lin, IC Design of Analog Min-Sum Decoder for (8,4) Regular LDPC Codes, Master thesis, National Taipei University of Technology, Taipei, Taiwan, July 2008.

[42]Ming-Jiun Liu, IC Design of A Decision Device for Analog Viterbi Decoder, Master thesis, National Taipei University of Technology, Taipei, Taiwan, July 2005.

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