數位式鎖相迴路振盪器之研製

The Study and Implementation of Digital Phase-Locked Loop Oscillator

葉茂盛(Mao-Sheng Yeh)

指導教授 ： 楊正任

元智大學/工程學院/電機工程學系/碩士(2000年)

摘要

本論文係利用全數位鎖相迴路的架構及原理，設計一鎖相迴路振盪器。在此系統中我們發展一“經修飾相位比較器（modified phase detector）”取代傳統相位比較器，並以電腦模擬設計整個系統，評估各參數與系統間的關係，特別是將以理論解析使用比例控制器或比例微分控制器來實現數位迴路濾波器之可行性，並以比例控制器之模擬結果進行鎖相迴路振盪器硬體設計與製作。
此數位鎖相迴路振盪器雖有較大的雜波與較大的相位雜訊，無法用在通訊的本地振盪源，但可程式化的優點使我們可以將它應用在我們所構思之壓控振盪器測試系統或馬達定速，為使我們所構思之壓控振盪器測試系統面對各式各樣的壓控振盪器皆能夠穩定並有良好的特性，我們需要一可程式的鎖相迴路，使其在測試不同壓控振盪器時可給定不同的參數，因此可利用我們所設計的數位式鎖相迴路振盪器滿足其需求。
本論文亦完成壓控振盪器測試系統之硬體製作，其測試原理係利用單晶片微電腦指揮鎖相迴路系統，迫使鎖相迴路鎖定待測之壓控振盪器於特定頻率，並由鎖定指示電路回報給單晶片微電腦是否已經鎖定，一旦確定系統已鎖定，則單晶片微電腦將讀取數位迴路濾波器輸出之數位調控電壓，改變特定頻率並重複前述之測試程序即可測得微波壓控振盪器在不同調控電壓下之振盪頻率。

關鍵字

鎖相迴路 ； 全數位式鎖相迴路鎖相迴路 ； 壓控振盪器測試系統

並列摘要

In this thesis, we develop a digital phase-locked loop oscillator based on the theory of all-digital phase-locked loop (ADPLL). We propose a “modified phase detector” to replace a tradition phase detector. The design of the negative feedback system is theoretically simulated. We evaluate the system response with difference system parameter. Especially we use the theory to analyze the performance of digital loop filter with P controller or PD controller, and we practically implement the digital phase-locked loop oscillator with P controller.
The digital phase-locked loop oscillator perform high spurious and high phase noise, so It is not suitable for local oscillator in communication application, but with the advantage of programmable loop filter, it can be applied to voltage-controlled oscillator (VCO) testing system or motor speed controlling system. The new idea for VCO testing is based on ADPLL technique. In order to test all kinds of VCOs, we need a programmable PLL to maintain the feedback system stably and properly. Therefore, we apply the ADPLL technique to VCO testing system.
In this paper, we also practically implement the VCO testing system. The microprocessor controls the ADPLL system to force the DUT (VCO) to be locked in a designated frequency. If the tested VCO is locked at this frequency correctly, then the lock indicator will send the locking signal back to the microprocessor. The microprocessor will then receive the output voltage data of the loop filter. The microprocessor repeats the same procedures at the next testing frequency. The microprocessor will then record the oscillating frequency with different tuning voltage.

並列關鍵字

phase-locked loop ； all digital phase-locked loop ； VCO testing system

參考文獻

2. Michael J. Werter, ”A Digital Phase-Locked Loop for Frequency Detection,” IEEE Tran. on Circuit and system, pp.1252 — 1255, 1996.

3. Byungjin Chun, Seung Hee Choi, and Beomsup Kim, “A Digital Phase-Locked Loop with Variable Loop Gains Derived from RLS Method” IEEE Tran. on Communications, vol. 45 , pp. 11-15, 1997.

4. Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee, “Fuzzy Logic for Digital Phase-Locked Loop Filter Design ” IEEE Tran. on Fuzzy System, Vol. 3, No. 2, pp.211-218, May 1995.

7. 陳泓誠, “Realization of Frequency Synthesizer and Voltage Control Oscillator Worked at Low Voltage for Wireless Communications” 元智大學碩士論文, 1998

8. Benjamin C. KUO, “Automatic Control System.”Wiley ,Seventh Edition.