應用於專用短距離通訊系統之低功耗高線性度混頻器設計

Low Power Consumption and High Linearity Mixer Design for DSRC Applications

黃志文(Chih-Wen Huang)

指導教授 ： 黃建彰

元智大學/電機通訊學院/通訊工程學系/碩士(2013年)

https://doi.org/10.6838/YZU.2013.00353

摘要

本論文講述應用於專用短距離通訊系統之低功耗高線性度之混頻器設計。此混頻器使用臺積電提供之0.18 um CMOS 1P6M 製程。本設計使用類似Gilbert-cell架構作雙平衡操作，為取得較佳的雜訊指數與線性度特性，將其設計成電阻性混頻方式，並將本地振盪訊號從基底／源極端輸入，利用基底注入技術降低混頻器的功耗以及本地振盪所需功率。
電路經量測，在降頻模式中，混頻器的轉換損耗為16.26 dB，輸入 1 dB 壓縮點 1.5 dBm，輸入三階截斷點為 13 dBm，雜訊指數與功耗分別為15.41 dB與0.16 mW；在昇頻模式中，混頻器的轉換損耗為18.53 dB，輸入/輸出 1 dB 壓縮點分別為-4.5 dBm以及-13 dBm，輸入與輸出三階截斷點點分別為-3 dBm以及-7 dBm。

關鍵字

混頻器 ； 專用短距離通訊系統 ； 功耗 ； 線性度 ； 電阻性

並列摘要

This paper presents a low power consumption and high linearity mixer design for dedicated-short-range-communications (DSRC) applications. The designed mixer is in the double-balanced configuration similar to the Gilbert-cell structure, The mixer core is worked at the triode region to perform the resistive mixing for better noise figure and linearity, the local oscillator (LO) signal is applied to the bulk and the source terminals in order to use the bulk-injection method to reduce the required LO power and dc power consumption.
In the down-convert mode, the measured conversion loss and input 1-dB compression point are about 16.26 dB and 1.5 dBm, the input third-order intercept point (IP3) of 13 dBm, the noise figure and power consumption are about 15.41 dB and 0.16 mW; in the up-convert mode, the measured conversion loss is about 18.53 dB, the input and output 1-dB compression point are about -4.5 dBm and -13 dBm, the input and output IP3 are about -3 dBm and -7 dBm.

並列關鍵字

Mixer ； DSRC ； Power Consumption ； Linearity ； resistive

參考文獻

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