十六通道腦電波訊號擷取晶片之研製

Design of a 16-Channel EEG Signal Acquisition Chip

林能毅(Neng-Yi Lin)

指導教授 ： 蔡育秀

中原大學/工學院/醫學工程研究所/碩士(2002年)

https://doi.org/10.6840/cycu200200532

摘要

在人體所有的生理訊號中，腦電波（EEG）訊號的量測算是相當困難的一環。腦電波意指腦部神經活動的綜合變化，一般在大腦皮層所量到的振幅約為10mV，在經過顱骨及電極片後便衰減到約為0.1uV〜100uV的大小。由於腦波訊號非常微弱，也非常容易被受測者本身、量測環境及電路本身等因素所影響。故本研究旨在設計一個十六通道腦波訊號擷取晶片，將所有前端類比電路整合於單一晶片中，除可減少十六通道所需大量元件之成本、接線的複雜度外，亦可降低因複雜的接線對腦波在量測時所造成的干擾，使後端作處理及分析的訊號品質能夠更為精確。

本研究所設計的腦波訊號擷取晶片包含了16組電流式儀表放大器（CMIA）及交換電容濾波器（SCF）、一個非重疊時脈產生器（Nonoverlapping Clock Generator）及16-to-1的類比多工器、可程式增益放大器（PGA）等電路。另外顧及到採用SCF濾波後的訊號品質，所以在SCF的前後端分別加入反混淆濾波器（Anti-aliasing Filter）及平滑濾波器（Smoothing Filter），讓經過濾波電路的訊號降低失真的可能性，使得輸出訊號更為可靠。整個電路設計之流程是採全客戶設計方式（Full-Custom Design），並用UMC 0.5μm CMOS 2P2M製程技術來實現，所設計之電路皆經模擬確定符合規格後，才進行最後的晶片佈局。

為驗證所規劃的架構能滿足腦波訊號處理之需求，故採用K-Complex EEG作為模擬的輸入訊號源，用以評估所設計電路之可行性。經本研究的實驗證明，將本系統積體化確實可行，並可達到縮小體積、使用方便等優點。

關鍵字

腦電波 ； K複合波 ； 平滑濾波器 ； 非重疊時脈產生器 ； 交換電容濾波器 ； 電流式儀表放大器 ； 反混淆濾波器

並列摘要

Among the physiological signals, due to its relative low amplitude non-stationary properties, the Electroencephalogram (EEG) is thought to be the most difficult to measure. In general, the amplitude of EEG in the cortex is about 10mV, but decreased to 0.1uV~100uV after passing through the cranium and skull. The patient oneself, environment and circuit layout affect the measured EEG signal quality easily. The objective of this research is to design an analog integrated circuit chip for a sixteen-channel EEG acquisition. The design is suitable for an analog front-end circuit of a portable EEG acquisition. By reducing the number of circuit component and noise, it can greatly enhance the signal quality to insure a better signal-to-noise ratio for preceding signal process and analysis tasks.

The main blocks of the EEG acquisition chip includes 16 current-mode instrumentation amplifiers (CMIA), 16 switched-capacitor filters (SCF), one non-overlapping clock generator, one 16:1 analog multiplexer, and one programmable gain amplifier (PGA). By placing an anti-aliasing filter and a smoothing filter before and after the SCF circuit, respectively, the distortion caused by the SCF circuit is dramatically improved. Hence, we can get the reliable signal in this circuit structure. These circuits have been fabricated with standard CMOS IC process of UMC 0.5μm CMOS double poly double metal. Full custom design flow has been used in this research. Before the layout of chip, these circuits has simulated by the HSPICE.

In order to evaluate the performance of these designs, a K-complex of normal sleep EEG is used as the input source to the EEG chip. The results demonstrate that it meets the system specifications. It is proved that by the integrating method, the System-On-a-Ship (SOC) approach for the medical instrumentation design is feasible.

並列關鍵字

EEG ； Anti-aliasing Filter ； K-Complex ； Non-overlapping Clock Generator ； SCF ； Smoothing Filter ； CMIA

參考文獻

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