同步尋找轉態延遲及電晶體固定開路之加強型掃描測試圖樣

Enhanced-Scan Test Generation for Both Transition Delay and Stuck-Open Faults

張展魁(Chan-Kuei Chang)

指導教授 ： 梁新聰

中原大學/工學院/電子工程研究所/碩士(2010年)

https://doi.org/10.6840/cycu201000692

摘要

本研究同時考慮轉態延遲障礙(transition delay fault, TDF)與電晶體固定開路障礙(stuck-open fault, SOF)，提出產生其測試圖樣方法以應用於加強型之掃瞄測試設計電路中。首先分析各種邏輯閘轉態延遲及固定開路兩種障礙分別需要之測試圖樣，由其中的關係找出最優先及次要優先的測試圖樣參考資料。針對原電路之組合電路部份，本方法藉由SAF測試圖樣建立出其驅動向量(activation vector, AV)，依據此驅動向量產生相對應的啟動向量(initialization vector, IV)。程式實現過程中，使用greedy壓縮與障礙模擬，以減少測試圖樣數量。依照此方可以判斷出那些TDF或SOF為可測得或不可測得。最後我們使用ISCAS89 全部電路產生測試圖樣，其障礙涵蓋率(fault coverage)與測試效能(test efficiency)都有很好的表現。

關鍵字

固定開路障礙 ； 轉態延遲障礙 ； 測試圖樣

並列摘要

In this thesis, we propose a method of the test pattern generation for enhanced-scan circuits which is considered transition delay fault and stuck-open fault simultaneously. Firstly, we analyze the test pattern of transition delay fault and stuck-open fault in primitive gates and define the priority. In the process, we establish the activation pattern by stuck-at fault patterns for the circuit in combinational part. According to the activation pattern, the corresponsive initialization pattern can be generated. We also use the greedy compression and fault simulation to reduce the test pattern count. The method can define which transition delay fault or stuck-open fault is testable fault or untestable fault. Finally, Using all of the ISCAS89 benchmark circuits to generate test patterns, and the experiment results has excellent performance for fault coverage and test efficiency.

並列關鍵字

transition delay fault ； stuck-open fault ； test pattern

參考文獻

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[4] J. Leenstr, M. Koch, T. Schwederski, “On Scan Path Design for Stuck-Open and Delay Fault Detection,” in Proc. of 3rd European Test conf., pp.201-210, 1993.

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