基於快速傅立葉轉換之雙算術邏輯運算單元數位訊號處理器設計

The Chip Design of FFT-Based Dual-ALU Digital Signal Processor

朱振緯(Zhen-Wei Zhu)

指導教授 ： 吳俊德

國立暨南國際大學/科技學院/電機工程學系/碩士(2007年)

https://doi.org/10.6837/NCNU.2007.00261

摘要

本篇論文提出一顆可以應用於多媒體系統的數位訊號處理晶片。在該處理器中，包含了兩個核心:快速傅立葉轉換特殊積體電路與雙算術邏輯運算單元數位訊號處理器。於快速傅立葉轉換特殊積體電路中，為了降低晶片的功率消耗以及計算量，我們採用一種新的暫存器陣列方法並使用二維管線式的架構來設計。另外，雙算術邏輯運算單元數位訊號處理器方面，我們將設計雙算數邏輯運算單元，此一特殊架構，用於增快語音辨識處理功能，其可有效的將運算之工作分配給兩顆ALU，使該晶片具有平行運算能力，以加強處理數位訊號之能力。此處理器中，我們應用TSMC 0.13um 標準單元(standard cell)合成出處理器電路，處理器晶片面積約為2.8x2.82mm，工作頻率為100MHz。

關鍵字

嵌入式系統 ； 雙算數邏輯運算單元 ； 管線式架構 ； 快速富利葉轉換特殊應用積體電路

並列摘要

This paper proposed the chip design of digital signal processer. It is composed by two cores: a low-power high performance fast fourier transform (FFT) ASIC and a dual-ALU digital signal process (DSP) processor. In the FFT processor, we proposed a novel register array based pipelined radix-2 structure to reduce power consumption and computation cycles. In the dual-ALU DSP processor, we use hardware-software co-design methodology to optimize the processor architecture and instruction set. The dual-ALU architecture provides parallel calculation capability. This novel architecture chip can reduce more power consumption and computation cycle. The processor is synthesized by TSMC 0.13um cell library. The die size is 2.8x2.8mm2. Working frequency is 100MHz.

並列關鍵字

EMBEDDED SYSTEMS ； Dual-ALU ； Pipeline ； spatial application VLSI circuit of FFT

參考文獻

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