前饋式雙取樣三位元四階帶通差和調變器設計

THE DESIGN OF A DOUBLE-SAMPLED 3-BIT FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR BASED ON THE FEEDFORWARD TOPOLOGY

廖敏雄(Min-Hsiung Liao)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2005年)

摘要

帶通差和調變器已經廣泛被運用在射頻通訊系統及測量儀器的製造，主要是因為帶通差和調變器比傳統的Nyquist-rate轉換器更能達到較高的解析能力。單位元量化的差和調變有著先天性的優勢，但可惜的是其產生的量化誤差相當大。因此可以使用多位元的量化方式來降低量化誤差，但前提是來自DAC元件不匹配所產生的誤差也就是非線性的缺陷能被解決。
前饋式帶通差和的架構比傳統的架構擁有幾項重要的優點。如前饋式架構較容易實現多位元量化的功能，不需要太複雜的電路並且實現之後的晶片面積較小。另外，利用雙取樣技術不僅能輕易地增加取樣頻率且還可舒緩對放大器的規格要求。
在本篇論文中，我們提出一前饋式架構為基礎之雙取樣三位元四階帶通差和調變器設計，其設計流程及相關設計軟體如下：先使用MATLAB模擬理想之系統層級電路，藉此得到最佳化的參數值。接下來用HSPICE模擬電晶體層級的電路，這樣可以加速整個設計的流程。此調變器的時脈頻率為50MHz(相當於100MHz的取樣頻率)，輸入中心頻率為25MHz、頻寬1.25MHz的訊號，以HSPICE所做的模擬結果顯示，在最佳化架構下，其訊號雜訊比在輸入為 -9 dBFS是60.58dB、消耗功率為155.2mW。此電路是使用TSMC 0.35μm CMOS 2P4M製程參數進行模擬。

關鍵字

四階帶通 ； 前饋式 ； 差和調變

並列摘要

Bandpass ΔΣ converters have been used widely in RF communication systems and instrumentation filed due to the ability to obtain high resolution in the band of interest compared to the traditional Nyquist-rate converters. Delta Sigma modulation with a single-bit quantizer is inherently linear, but unfortunately also causes the quantization noise power to be quite large. It can be reduced by using a multi-bit quantizer if the nonlinearity error introducted by component mismatches of DAC can be solved.
Feedforward delta-sigma topologies have important system- and circuit- level advantages over traditional topologies. It is easy to implement multi-bits with less complexity and physical area for this topology. Additionally, double-sampled switched-capacitor (SC) technique provides a good method of increasing the sampling frequency without many efforts and relaxes the requirement of the Opamp.
In this thesis, a double-sampled 3-bit fourth-order bandpass delta-sigma modulator based on the feedforward topology is proposed. The design flow corresponding to the CAD tools is as followings. Using MATLAB, the optimal parameters are obtained by the system-level simulation. Then, the transistor level simulation with foundry device model is implemented by HSPICE. Finally, the layout of the whole circuit is accomplished with Virtuoso of CADENCE. The clock frequency is 50MHz (effective frequency would be 100MHz). The input signal bandwidth is 1.25MHz centered at 25MHz. The simulation results using HSPICE present a SNR of 60.58dB with -9dBFS input and power consumption of 155.2mW. The modulator is simulated by using the SPICE models of TSMC 0.35μm CMOS 2P4M process.

並列關鍵字

BANDPASS ； DELTA-SIGMA MODULATOR ； FEEDFORWARD ； FOURTH-ORDER

參考文獻

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