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  • 學位論文

俱相關相位消除技巧之5-GHz小數型頻率合成器

Design of a 5-GHz Relative-Phase Cancellation Fractional-N Frequency Synthesizer

指導教授 : 林宗賢
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摘要


在無線通訊系統中,頻率合成器扮演重要的角色,無論是發射機、傳輸機,都需要頻率合成器來產生本地震盪頻率。而且,發射機之實現也可單獨藉由在鎖相迴路式頻率合成器之迴路內部調變來達成。在控制除數來調變壓控振盪器的方式中,雖然擁有較低的能量消耗和較少的電路元件,但頻率合成器的迴路頻寬限制了發射機的資料傳輸率。所以如何增加頻率合成器的頻寬是本論文主要探討的課題。 在本論文中,提出了一個新的電路方法,稱為相關相位消除技術。使用一個除頻器陣列來產生相關相位。兩組電流幫浦可由數位訊號來控制電流比例,然後消除相關相位。沒有被如三角積分調變架構頻率合成器出現的量化誤差雜訊所困擾,所以能夠達到較寬的迴路頻寬。最後,量測結果顯示,此頻率合成器鎖定在4.8-GHz,並且在100-kHz之迴路頻寬、參考頻率為25-MHz之條件下,達到-49 dBc的小數突波。此時,整個頻率合成器功率消耗在1.2 V的電壓供應之下花了17毫瓦。

並列摘要


A frequency synthesizer plays an important role in wireless communication system. Both transmitter and receiver need the synthesizer to generate local oscilation frequency. In addition, a transmitter can be implemented by utilizing the in-loop modulation of a phase-locked loop (PLL) based frequency synthesizer. In the technique of indirectly modulating the VCO by varying the divide value, although it has lower power consumption and less circuit components, the transmitter’s transmission data rate is restricted within the loop bandwidth of frequency synthesizer. Thus, widening the loop bandwidth can be a challenging design problem in this thesis. In the thesis, a new approach is called “relative-phase cancellation” (RPC) technique. The relative phase is made a divider array, and the charge pump current ratio is controlled by digital code. Thus, the relative phase can be cancelled. The RPC technique can achieve wide bandwidth, because there is no quantization noise which appears in delta-sigma fractional-N frequency synthesizer. Finally, the measurement results reveal that the RPC frequency synthesizer is locked at 4.7-GHz, and it achieves a magnitude of -49 dBc fractional spurs with a 100-kHz loop bandwidth and a 25-MHz reference frequency. The measured power consumption with a 1.2-V supply voltage is about 17 mW.

參考文獻


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