產生任意寬域延遲之低抖動去偏斜時脈產生器與全數位連續資料速率寬追蹤範圍之時脈資料回復電路

本篇論文包含兩個已執行在標準CMOS製程的積體電路晶片，一個是延連鎖相迴路，另一個是時脈資料回復電路。延連鎖相迴路已經被廣泛的利用在高速記憶體介面電路和時脈倍頻器和多相位時脈產生器以及用來去時脈的偏斜.比起傳統的相位鎖定迴路，延連鎖相迴路有兩個主要的優點。第一個是快速鎖定，另一個是無條件穩定。在些論文的前半部分，提出的是一個任意寬域延遲去偏斜時脈產生器，輸入頻率為300到800百萬赫茲。此延連鎖相迴路在0.18微米中實現。並達到低抖動、低功率消耗、低面積之特性。隨著資料傳輸的快速發展，在超過好幾十億赫茲操作速率的通訊系統要求更低的成本。傳輸的介質資也因為追求更高的頻寬逐漸的從銅線演變成光纖。時脈資料回復電路移除資料的抖動並回復資料給接下來的電路使用。在這個研究主題中從數位電路的的觀點詳盡的介紹研究和電路的實現。後半部分論文提出一個基於時間數位轉換器而設計的全數位寬追蹤範圍的時脈資料回復電路並於在90奈米中實現。些架構大大的增加了捕獲範圍。

關鍵字

時脈產生器；延遲鎖相迴路；時脈資料回復電路

並列摘要

This thesis contains two chips one is DLL the other is CDR implemented in standard CMOS technology. The delay locked loop (DLL) is widely used for high-speed memory interface circuits and clock multipliers to perform clock de-skew. The DLL offers two attractive advantages over conventional PLL: one is a faster locked time, and the other is unconditionally stability. First, half of this thesis proposed a 300- to 800-MHz low jitter and ringing effect free de-skew clock generator for arbitrary delay. The generator is designed and fabricated in a 0.18-μm CMOS process. The power consumption is 10mW at 800MHz. The rapid growth of data transmission demands low-cost communication systems operating at frequencies over several GHz. The pursuit for larger bandwidth converts the transmission medium from copper wire to fiber gradually. Clock and data recovery (CDR) circuits both remove the jitter in the data and retime the data for the succeeding circuits. A complete investigation and implementation of this CDR from a digital circuit point of view will be elaborated in this research. The other half of this thesis proposed a TDC-based all-digital wide capture range CDR and is implemented by standard 90-nm CMOS technology. The proposed architecture can increase the capture range.

並列關鍵字

Clock Generator ； DLL ； CDR

參考文獻

[1] J. G. Maneatiss, “Low-Jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.

[2] B. Razavi, “Design of Analog CMOS Integrated Circuits,” 1st Ed., McGraw-Hill, 2001.

[3] B. Razavi, "Design of Integrated Circuits for Optical Communications,” 1st Ed., Mc-Graw Hill, 2003.

[4] J.-H. Kim, Y.-H. Kwak, M. Kim, S.-W. Kim, and C. Kim, “A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling” IEEE J. Solid-State Circuits, vol. 41, pp. 2077-2082, Sep. 2006.

[5] H. Jin, and E. K. F. Lee, “A Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADC’s,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 7, pp. 603-613, Jul. 2000.

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產生任意寬域延遲之低抖動去偏斜時脈產生器與全數位連續資料速率寬追蹤範圍之時脈資料回復電路

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