切換電容導向之時鐘網路建構方法

時鐘網路的功率消耗是晶片全部功率消耗的主要來源之ㄧ。為了提升產品的可使用性，低功率的技術變得非常重要，尤其是對於時鐘網路的低功率設計方法。時鐘閘控是降低數位電路動態功率消耗的有效方法。當暫存器內儲存的值不需要改變時，可以藉著關閉時脈訊號的切換來降低切換電容的值。除此之外，利用限制時序差異的時鐘樹可以縮短時脈訊號的線路長度，這也暗示了可以達到更低的功率消耗。在本篇論文，我們將整合時鐘閘控及限制時序差異時鐘樹的方法去建構出一個擁有最小功率消耗的閘控時鐘樹。首先，我們提出一個時鐘樹拓樸生成方法來產生擁有最小輸出負載的時鐘樹拓樸。其次，我們利用限制時序差異時鐘樹的繞線演算法嵌入產生的時鐘樹拓樸。最後，我們使用動態規劃的方式來調整緩衝器的尺寸，以期望更進一步最佳化功率的消耗。實驗結果顯示我們的方法能有效的降低動態功率的消耗。

關鍵字

時鐘樹；時序差異；時鐘閘控；緩衝器尺吋設計；低耗能；超大型積體電路；實體設計

並列摘要

Power dissipation in clock network distribution is one of the major sources of total power dissipation on a chip. In order to increase utility of the products, low-power techniques become very important, especially for clock network construction. Clock gating is an efficient way of reducing dynamic power consumption in digital circuits. It reduces switched capacitance by turning off transitions on a clock tree when the triggered registers do not need to change their values. Besides, bounded-skew clock tree is proposed to shorten the total wirelength of a clock net, implying lower power dissipation. Our work in this thesis is to construct a minimal power gated clock tree by integrating these two schemes. First, we propose a topology generation method to generate the clock tree topology with minimal output net loading. Second, we apply the bounded-skew clock routing algorithm to embed the generated topology. Finally, we perform buffer sizing by a dynamic programming approach to further optimize the power dissipation. The experimental results show that the algorithm is effective in reducing dynamic power consumption.

並列關鍵字

clock tree ； clock skew ； clock gating ； buffer sizing ； low power ； VLSI ； physical design

參考文獻

[4] M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock Routing for High Performance ICs,” Proc. ACM/IEEE Design Automation Conf., pp. 573-579, 1990.

[5] J. G. Xi and W. W.-M. Dai, “Useful-skew Clock Routing with Gate Sizing for Low Power Design,” Proc. ACM/IEEE Design Automation Conf., pp. 383-388, 1996.

[6] C.-W. A. Tsao and C.-K. Koh, “UST/DME: A Clock Tree Router for General Skew Constraints,” Proc. ACM/IEEE International Conference on Computer-Aid Design, pp. 400-405, 2000.

[7] M. Edahiro, “An Efficient Zero-Skew Routing Algorithm,”Proc. ACM/IEEE Design Automation Conf., pp. 375-380, 1994.

[12] J. G. Xi and W. W.-M. Dai, “Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution,” Proc. ACM/IEEE Design Automation Conf., pp. 383-388, 1995.

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切換電容導向之時鐘網路建構方法

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