高速與低功耗CMOS微型等化器之研製

本論文提出一個超低功耗微型化20Gb/s被動混和主動式等化器以及一個創新的適應性偏壓20Gb/s等化器。第一個電路提出一個微型化且低功耗的被動混和主動式等化器，被動級等化器不僅僅分擔了主動級等化器在高頻的增益需求，更大大的降低了整體功耗。而為了微型化設計，此作品亦採用了三維被動電感與主動式電感的技術。藉由台積90奈米製程，此作品僅耗費10.8mW功率和0.017mm2面積。補償完180公分的同軸纜線後在22Gb/s的量測中最大的峰對峰抖動值為19ps。在針對適應性等化器的研究中，第二個電路提出一個創新的適應性偏壓等化器。此種藉由適應性偏壓微調的機制可以簡化傳統回授控制的設計複雜性，消除在雙迴圈控制下會產生的衝突問題，克服比較器的速度限制以及省去迴圈控制電路裡所有額外消耗的面積與功耗。克服了所述適應性等化器的難題，此作品在11GHz的頻率下分別補足了7dB、9dB和11dB的損耗，其量測的最大峰對峰值抖動分別約為9ps、11ps和23ps。

關鍵字

等化器；適應性偏壓

並列摘要

In this thesis, an ultra-low-power miniature 20Gb/s passive/active hybrid equalizer and a novel 20Gb/s adaptive bias equalizer are proposed. In the first work, a compact and low-power passive/active hybrid equalizer is presented. By sharing the loading of high frequency peaking with the active equalizing stage, the passive filtering stage reduces the power significantly. To achieve a small area, the 3D inductor and active inductor techniques have also been incorporated in this design. Implemented in a standard 90 nm CMOS process, this passive/active hybrid equalizer has a very small power consumption of 10.8 mW and occupies a core chip area of only 0.017mm2. It can successfully equalize for the data transmitted through 180-cm coaxial cable line up to 22Gb/s in the measurement, where the peak-to-peak jitter is about 19 ps. In the second work, a novel adaptive bias equalizer is proposed. By adopting adaptive bias control circuit, the equalization is able to fulfill adaptive compensation without using a complex feedback loop. The proposed scheme also eliminates the conflict problem in traditional dual loop control, the speed limitation of comparator, and all the additional circuits in the servo loop. The proposed adaptive bias equalizer is able to transmit 22Gb/s data for a cable loss of 7dB, 9dB, and 11dB at 11GHz, where the peak-to-peak jitter is about 9ps, 11ps and 23ps, respectively.

並列關鍵字

Equalizer ； Adaptive Bias

參考文獻

[1] W. J. Dally and J. Poulton, "Transmitter equalization for 4-Gbps signaling," Micro IEEE , vol. 17, no.1, pp. 48-56, Jan. 1997.

[2] J. N. Babanezhad, "A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication," in Proc. IEEE Custom Integrated Circuits Conference, May 1998, pp.343-346.

[3] J. S. Choi, M. S. Hwang and D. K. Jeong, "A 0.18-μm CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp .419-425, Mar. 2004.

[4] S. Gondi and B. Razavi, "Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011, Sept. 2007.

[5] J. Lee, "A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology," IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058-2066, Sept. 2006.

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高速與低功耗CMOS微型等化器之研製

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