全數位時脈資料回復器及全數位鎖相迴路

All-digital Clock and Data Recovery and All-digital Phase-locked Loop

陳易楓(I-Fong Chen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.10329

摘要

近幾年來，在製程的定位上都是以減少電晶體尺寸為主，這可使電路設計上得到更高的操作頻率和更少的功率消耗，卻不利於類比電路設計，反之，更適合數位電路設計，因此已有許多的類比電路改以數位方式實現，例如，鎖相迴路和資料時脈回復電路。
在論文中，1.25Gbps全數位資料時脈回復電路被提出，由於累加器時脈頻率的限制，因此提出由預先累加器和具有定標器的路徑(第一積分路徑)來降低累加器的時脈頻率及迴路延遲，藉由降低迴路延遲可使用較小的正比路徑增益來獲得較低的時脈抖動，卻不會犧牲相位邊限，且與未具有第一積分路徑的迴路比較，又可增加阻尼係數和迴路頻寬。在所提出的1.25 Gbps全數位資料時脈回復電路其時脈抖動為51.1ps且錯誤率皆低於10-12，功率消耗和主動元件面積分別為23.4mW和0.423mm2。
在論文中，1.25GHz全數位鎖相迴路被提出，一個二位元型態的全數位鎖相迴路需要較長的頻率獲取時間，因為相位頻率偵測器的輸出僅為+1和-1，故提出一個有效的減少頻率獲取時間的演算法，在全數位鎖相迴路中數位控制振盪器對於電源雜訊有最大影響，因此提出迴路頻寬調校電路來決定可使時脈抖動為最小的頻寬，其利用時間窗(timing window)來偵測時脈抖動調整頻寬。在提出的1.25 GHz全數位鎖相迴路其時脈抖動為38.9ps且相位雜訊在1MHz偏移時為-103.22dBc/Hz，功率消耗為9mW，而主動元件面積為0.348mm2。

關鍵字

全數位時脈資料回復器 ； 全數位鎖相迴路

並列摘要

In recent years, the orientation of the fabrication process is to shrink the scaling of the transistor. Scaling down the transistor will have less power consumption and faster operation frequency to design circuits. However, it has extra drawbacks for analog circuits, but it is more suitable for digital circuits. Therefore, digital equivalent implementations of analog circuits are more popular, such as the phase-locked loop and the clock and data recovery.
In this thesis, a 1.25 Gbps all-digital clock and data recovery is proposed. The clock frequency of the accumulator is too slow. The proposed pre-accumulator and the path with the scaler (the first integral path) are used to slow down the clock frequency of the accumulator and reduce the loop latency. By reducing the loop latency, the smaller is used to have low jitter performance without sacrificing the phase margin. Compared with the loop without the first integral path, it also increases the damping factor and the bandwidth. The jitter of the proposed 1.25Gbps all-digital clock and data recovery is only 51.1 ps and its bit error rate is below 10-12. The power consumption is 23.4 mW and the core area is 0.423mm2.
In this thesis, a 1.25 GHz all-digital phase-locked loop is proposed. The bang-bang type all-digital phase-locked loop needs long frequency acquisition time because the phase/frequency detector only has binary outputs, and. The proposed algorithm can effectively reduce the frequency acquisition time. The supply noise toward the DCO has severely impact in the all-digital PLL. Therefore, the proposed bandwidth calibration circuit decides the bandwidth which make the all-digital PLL have the lowest jitter by using the timing window measuring the jitter to change the bandwidth. The jitter of the proposed all-digital phase-locked loop is 38.9 ps and the phase noise is -103.22dBc/Hz at 1MHz offset. Its power consumption is 9 mW and the core area is 0.348mm2.

並列關鍵字

ADCDR ； ADPLL

參考文獻

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