低功率之高效能動態邏輯電路設計

A Conditional Isolator Technique for Wide Pseudo-Footless Domino Logic Circuits

邱威豪(Wei-Hao Chiu) ； 葉重廷(Tsung-Ting Yeh) ； 林浩仁(How-Rern Lin)

《科學與工程技術期刊》 4卷1期 (2008/03) Pp. 11-17

https://doi.org/10.7117/JSET.200803.0011

摘要

漏電流(leakage current)在深次微米與奈米電路的設計中是一個相當重要且又棘手的問題；這種現象使得不必要的電能耗損變得相當嚴重。在本篇論文中，我們針對Pseudo-Footless骨牌式電路提出Conditional Isolator的設計技術，可以進一步將動態節點(dynamic node)與下拉邏輯迴路(pull-down network, PDN)隔離開來，在不犧牲整體電路速度的前提下，減少Pseudo-Footless骨牌式電路於運算週期的不必要功率消耗問題。根據於32輸入OR閘的實驗結果顯示，相較於Pseudo-Footless骨牌式電路與傳統骨牌式電路，Conditional Isolator技術可以顯著改善漏電流所引起的功率消耗達到80%。

關鍵字

漏電流 ； Pseudo-Footless骨牌式電路 ； 動態電路

並列摘要

Leakage current is a critical issue in the design of very deep submicron circuits, causing serious unnecessary power consumption. In this study, we propose a Conditional Isolator design technique for wide fan-in domino circuits. This Conditional Isolator can circumstantially separate the dynamic node from a Pull-Down Network (PDN) and reduce unnecessary power consumption during the evaluation cycle in Pseudo-Footless Domino logic without sacrificing performance. From the results of an experimental simulation on 32-input OR gates, it is shown that the Conditional Isolator technique can achieve more than 80% improvement in leakage power when compared to that of conventional footless and robust Pseudo-Footless Domino gates..

並列關鍵字

leakage current ； pseudo-footless domino logic ； dynamic circuit