2007年發表了一篇以臨界偵測電路為基礎之管線式類比數位轉換器,取代了在傳統方法中所需要使用到的運算放大器。此架構的基本概念為利用一個偵測虛短路的比較器以及定電流源,取代利用負回授迫使虛短路的運算放大器。這個架構最原始的雛形是單端式的管線式類比數位轉換器、並達到了每秒兩億次的取樣速度。而為了抵抗電壓供應源以及基板的雜訊,以臨界偵測電路為基礎架構之全差動管線式類比數位轉換器於2009年發表,達到了每秒五千萬次的取樣速度,然而取樣速度卻被臨界偵測電路的本質延遲時間所限制住。本論文提出了「比較器延遲消除」技術用以打破取樣速率的限制。此外,本論文也提出了「增益誤差修正」的技術來解決「比較器延遲消除」技術所衍伸出一的增益誤差問題。結合上述所提到的兩項技術,本論文在九零奈米的製程下實現了一個八位元、每秒三億六千萬次取樣、全差動管線式類比數位轉換器,此轉換器達到了38.98dB的SNDR以及47.19的無雜訊動態範圍(SFDR),其功率消耗在1伏特的供應電壓下為28毫瓦特。本論文使得以臨界偵測電路為基礎架構之全差動類比數位轉換器的取樣速度可以達到理論上的最大值,實現了以臨界偵測電路為基礎之高速全差動類比數位轉換器。
A zero-crossing based circuits (ZCBC) topology published in 2007 had been substituted for the conventional operational amplifier (opamp) based pipelined ADCs. The concept of ZCBC technique is to replace an opamp with a threshold-detection comparator and a ramp generator, which is able to detect virtual ground rather than using negative feedback to force it. The original ZCBC prototype realizes a single-ended pipelined ADC which achieves 200MS/s. To enhance the power supply rejection, a fully-differential ZCBC pipelined ADC was proposed with 50MS/s in 2009. However, the sampling rate of fully-differential ZCBC pipelined ADC is limited by intrinsic delay time of threshold-detection comparator. This research proposes a “comparator delay cancelling (CDC) technique” to break the limitation of sampling rate of the fully-differential ZCBC pipelined ADC. Moreover, this research also offers a “gain-error correction (GEC) technique” to solve the gain error problem which is induced by the CDC technique. By Combining the CDC and GEC techniques, this research realizes a 360MS/s fully-differential ZCBC pipelined ADC in 90nm process. This ADC achieves the performance of 38.98dB SNDR, 47.19dB SFDR, and consumes 28mW from 1V power supply. In addition, it obtains a figure-of-merit (FOM) of 1.06pJ/step. In conclusion, this design achieves the highest sampling rate in fully-differential ZCBC architecture, validating the prototype of high speed fully-differential ZCBC pipelined ADC.