新型類比式(8,4)疊代遞迴最小－和低密度奇偶校驗解碼器之晶片設計

Chip Design of Novel Analog Min-Sum Iterative Decoder for a (8,4) Low-Density Parity-Check (LDPC) Decoder

王惠生(Huei-Sheng Wang)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2008年)

摘要

在本論文我們設計出一顆能直接讀取類比訊號的類比式通道解碼器，它可取代了傳統的數位－類比轉換器及數位解碼器。而類比解碼器的主要優點，它沒有像數位解碼器需要大量的記憶體及靜態消耗的功率，故其體積及功率消耗可以大幅降低。
其中我們是以威爾森電流鏡來取代傳統疊接電流鏡，其擁有低輸入電壓擺幅Vtn + VODn < Vin < VDD －（|Vtp| + |VODp|）及較大工作頻寬的優點，實現以最小－和演算法為基礎的類比式低密度奇偶校驗解碼器。在本論文中所設計之新型類比式LDPC解碼器是採用TSMC 0.35-μm Mixed-Signal 2P4M Polycide 3.3/5V的製程技術，此晶片設計由2352顆電晶體組成，輸入電流範圍為－7μA~7μA，核心面積為1.36 mm2且含I/O PAD的晶片面積為3.22mm2，消耗功率為22.9mW，核心架構的輸入及輸出訊號分別為類比與數位訊號，輸入位元為8×4bits，輸出為8bits。此晶片設計具有低功率消耗、低面積、及容易與前端解調變電路結合，未來可供新型通訊系統晶片應用。

關鍵字

類比解碼器 ； 低密度奇偶校驗碼 ； 最小－和演算法 ； 威爾森電流鏡

並列摘要

In this thesis, we have designed an analog decoder that directly received analog signal using min-sum low-density parity-check (LDPC) code. To verify our method, we have finished a novel analog min-sum iterative decoder for a (8,4) low-density parity-check decoder chip with TSMC 0.35-μm Mixed-Signal 2P4M Polycide CMOS technology.
In the LDPC decoder chip, we used Wilson current mirrors to replace cascode current mirrors in the variable node. This chip contains 2352 transistors, using a single 3.3-V power supply and consumes 22.9mW. The chip area including pads is about 3.22mm2, and core area is about 1.36 mm2.This chip has the advantages of low-power, small area, low-cost, and it can provide an efficient design for future SOC communications.

並列關鍵字

Analog Decoder ； Low-Density Parity-Check code ； Mini-Sum Algorithm ； Wilson Current Mirror

參考文獻

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