適合CMOS製程之MOS-NDR元件與電路的設計與應用

Design and Application of MOS-NDR Devices and Circuits Suitable for CMOS Technology

郭士賓(Shin-Bin Kuo)

指導教授 ： 甘廣宙

崑山科技大學/工程學院/電子工程研究所/碩士(2004年)

摘要

一般學術界所謂的負微分電阻元件(Negative Differential Resistance, NDR)，指的是共振穿透二極體(RTD)，它是以化合物半導體的技術製作而成，其材料有高電子移動率等優點。目前負微分電阻元件，已被應用於一些電路設計上，例如：類比/數位轉換器(analog/digital converter)，加法器(adder)，多值多工器(multiple-value multiplexer)，邏輯電路(logic circuit)等應用電路上。
在本研究中我們所製作的負微分電阻元件，則是以金屬氧化半導體場效電晶體(MOS)元件所架構而成的，我們實現了以0.35μm 1P4M CMOS製程製作的負微分電阻元件的晶片，其結構是由三個N型MOS元件與一個P型MOS元件所構成，由於它是以MOS元件所組成，因此我們稱此負微分電阻元件為MOS-NDR元件。
我們藉由適當設計MOS元件的寬度、長度參數(Width / Length)，並控制其雙端電源電壓的大小，我們可得到具有不同的峰值(peak)與谷值(valley)的電流-電壓特性曲線(Current-Voltage characteristics)。所以此元件具有極廣大範圍的調變特性，對於其應用電路的設計與開發，深具研究價值。而此元件最大的優點，在於將我們可與國家晶片系統設計中心(CIC)所提供的CMOS與BiCMOS製程相配合，將此負微分電阻元件與應用電路相整合於同一矽(Silicon)晶片上，達到積體電路化(IC)與系統晶片化(SoC)的目標。
多峰值(Multiple-Peak)負微分電阻元件可以使以負微分電阻元件為基礎所設計的應用電路，例如多值邏輯與記憶電路，可縮減電路元件上的數目，使得電路設計變的更簡易。多峰值負微分電阻元件是以二組或多組負微分電阻元件串聯或並聯來組成。因此，在此論文中我們也詳述了多峰值負微分電阻元件的串聯與並聯的電路架構與原理。
在本論文中我們亦介紹了以單穩態-雙穩態傳輸邏輯閘(MOBILE)架構而成的多邏輯閘電路。所謂的單穩態-雙穩態傳輸邏輯閘，它是使用二組負微分電阻元件串聯在一起，藉由改變二組負電阻元件的電流-電壓特性曲線，而獲得數種不同邏輯閘輸出結果的電路原理。我們將在本論文中深入探討此理論與相關應用電路的設計。

關鍵字

單穩態與雙穩態傳輸邏輯閘原理 ； 負微分電阻元件

並列摘要

The general conventionally negative differential resistance (NDR) device is resonant-tunneling-diode (RTD) device. This RTD device is fabricated by the technique of compound semiconductor. This kind of NDR device is possessed of the high electron mobility. For the past years, the NDR device had been applied in some circuits such as analog/digital converter, adder, multiple-value multiplexer, and logic circuit.
However in our work, we proposed a new NDR device that is composed of metal-oxide-semiconductor field-effect-transistor (MOS) devices. Because this NDR device is consisted of three NMOS and one PMOS devices, we call this novel NDR device as MOS-NDR device. In experiment, we fabricate this MOS-NDR device by standard 0.35μm 1P4M CMOS process.
This MOS-NDR device could exhibit the NDR current-voltage (I-V) curve with different peak and valley just by suitably arranging the width and length parameters of the MOS devices. Therefore, this kind of device possessed a wide range of modulation in the I-V characteristics. Especially in the applied circuit design, this MOS-NDR device provided the convenience in consisted of other devices and circuits based on the Silicon substrate. These applications could be fabricated by the CMOS or BiCMOS technique that provided by the chip implementation center (CIC). So our proposed MOS-NDR device will be very useful in integrated circuit, and to achieve the system on a chip (SoC) subject.
The multiple-peak NDR devices provide a good opportunity to implement functional circuit such as multiple-valued logic and memory application with greatly reduced the circuit complexity and the number of devices. Numerous applications create the multiple-peak I-V characteristics with two or more NDR devices connected in series or in parallel. Therefore, we also analyzed, discussed, and fabricated the multiple-peak NDR devices in this work.
A monostable-bistable transition logic element (MOBILE), employing two NDR devices connected in series, is a functional logic gate. In our structure, two NDR devices connected in series, one of the NDR devices and a NMOS are connected in parallel. Therefore, the peak current of this NDR device can be controlled by means of an applied gate voltage of the NMOS device. For a two-input MOBILE gate, this implies the possibility of a variable function logic gate. We have proposed some logic circuits based on the MOBILE theory in this dissertation.

並列關鍵字

NDR ； MOBILE

參考文獻

[1] W. Williamson, III, S. B. Enquist, D. H. Chow, H. L. Dunlap, S. Subramaniam, P. Lei, G. H. Bernstein, and B. K. Gilbert, “12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gates,” IEEE J. Solid-State Circuits, vol. 32, 1997, pp. 222-230.

[2] T. Waho, K. Hattori, and Y. Takamatsu, “Flash analog-to-digital converter using resonant-tunneling multiple-valued circuits,” IEEE 0-7695-1083-3/01, 2001, pp. 94-99.

[3] S. J. Wei, H. C. Lin, R. C. Potter, and D. Shupe, “A self-latching A/D converter using resonant tunneling diodes,” IEEE J. Solid-State Circuits, vol. 28, June. 1993, pp. 697–700.

[4] A. F. Gonzalez and P. Mazumder, “Multiple-valued signed-digit adder using negative differential-resistance devices” IEEE Trans. Comput, vol. 47, Sept. 1998, pp. 947-959.

[5] M. Reddy, R. Y. Yu, H. Kroemer, “Bias Stabilization for Resonant Tunnel Diode Oscillators,” IEEE Microwave and Guided Wave Lett., vol. 5, July 1995, pp. 219-221.