低電壓製程之電荷幫浦電路設計

Charge Pump Design in Low-voltage CMOS Technology

翁怡歆(Yi-Hsin Weng)

指導教授 ： 柯明道

國立交通大學/電機學院/電機學院IC設計產業專班/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00787

摘要

電荷幫浦(charge pump circuits)能夠產生比輸入電壓(supply voltage)還要高的電位以及比基準電位(GND)還要低的電位。現今電荷幫浦主要用於非揮發性記憶體中(nonvolatile memory)，用來抹除資料或者是寫入資料，此外，為了能夠符合一般家用電規格，在LCD面板上同時也需要電荷幫浦來提高電壓以驅動面板的開關來達到色彩輸出。
因此，此篇論文提出一個新的電荷幫浦的架構，其目的是為了在沒有受到閘極可靠度(gate-oxide reliability)的影響之下，能夠減少漏電流(return-back leakage current)的產生，同時透過模擬以及實做來實現電路。透過量測可以驗證新的電路架構是否能正常工作以及是否有不錯的輸出效果。在1.8V的輸入電壓下，量測的輸出電位為8.8伏，此項結果可以驗證新的電路架構比傳統的電荷幫浦有較好的效能。同時也驗證在減少漏電流的情況以及沒有受到閘極可靠度的影響下，可以有效的提高輸出電壓。因此，新的電路架構是適合在現今的低電壓以及低功率的積體電路上。

關鍵字

電荷幫浦 ； 漏電流 ； 閘極可靠度 ； 低電壓

並列摘要

Charge pump circuits are usually used to generate voltages higher than the available supply voltage. It is applied widely in EEPROM or flash memories to program the floating-gate device.
A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate oxide reliability issue in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. By inserting a short turn-off period into the circuit operation of charge pump circuit, the return-back leakage current during the clock transition can be successfully suppressed in the new proposed charge pump circuit. The measured output voltage is around 8.8V with 1.8V supply voltage, which is better than the conventional charge pump circuit with the same pumping stages. Because of reducing the return-back leakage current and without suffering gate oxide reliability issue, the new proposed charge pump circuit is suitable for the applications in low-voltage and low-power CMOS IC products.

並列關鍵字

charge pump circuit ； leakage current ； gate oxide reliability ； low voltage

參考文獻

[2] J. F. Dickson, “ On chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplied technique,” IEEE J. Solid-State Circuits, vol. 1, pp. 374-378, Jun. 1976.

[4] S. Atsumi, M. Kuriyama, A. Umezawa, H. Banba, K. Naruke, S. Yamada, Y. Ohshima, M. Oshikiri, Y. Hiura, T. Yamane, and K. Yoshikawa, “A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation,” IEEE J. Solid-State Circuits, vol. 29, pp. 461-469, Apr. 1994.

[5] C. Yoo and K.-L. Lee, “A low-ripple poly-si TFT charge pump for driver-integrated LCD panel,” IEEE Trans. Consumer Electronics, vol. 51, No. 2, pp. 606-610, May 2005.

[6] J. S. Witters, G. Groeseneken, and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, pp. 1372-1380, Oct. 1989.

[7] K. Sawada, Y. Sugawara, and S. Masui, “An on-chip high-voltage generator circuit for EEPROM with a power supply voltage below 2V,” in Symp. VLSI Circuits Dig. Tech. Papers, 1992, pp. 75–76.