Title

具數位消除電路之四級MASH切換電流式三角積分調變器

Translated Titles

Fourth-order Switch-Current MASH Delta Sigma Modulator with Digital Cancellation Circuit

Authors

李念祖

Key Words

切換電流式 ; 三角積分調變器 ; 數位消除電路 ; delta-sigma modulator ; switched-current technique ; digital cancellation

PublicationName

臺北科技大學電機工程系所學位論文

Volume or Term/Year and Month of Publication

2013年

Academic Degree Category

碩士

Advisor

宋國明

Content Language

繁體中文

Chinese Abstract

三角積分調變技術對類比電路的非理想特性具有抵抗能力,數位電路處理之優點,因此在音頻訊號處理上表現優於其他類比架構,在語音處理、數位音響上該技術被廣泛應用。 本論文藉由製作四級MASH多級串接三角積分調變器來探討系統穩定度與相關積體電路之非理想效應的成因,並利用箝位電路消除輸入端非理想效應,採用低電壓設計改善切換電流式架構功耗過大的缺點,並找出切換電流式記憶元件擁有的優點及適合應用的方向。 本論文描述三角積分調變器基本原理,三角積分調變器從系統行為模式到電路實現,說明數位消除電路原理與設計,以及箝位電路特性分析。在系統電路的實現上,採用TSMC 0.18μm的互補式金氧半導體製程參數來設計與模擬。後模擬結果顯示,該四級MASH一位元多級串接架構,在提供電壓1.2伏特取樣頻率為5.12百萬赫(MHz)與超取樣率(OSR)為128的條件下,其有效頻寬為20仟赫,且其訊號雜訊比可達81分貝,相當於有效位元數約13.32位元,消耗功率為2.3毫瓦特。

English Abstract

The tolerant to the non-ideality of analog circuit and digital cancellation making Delta Sigma Modulator process audio signal much better and easier than other analog structure. Therefore, Delta Sigma Modulator has been widely used in digital audio and speech process. This thesis investgates a switched-current memory cell which is used in the high-order delta-sigma modulator., discussing what cause the non-ideality and the stability effect in the fourth order MASH delta-sigma modulator. To make the switching-current structure low power consumption , this thesis uses 1.2volt as supply voltage. The systematic simulation was completed with TSMC 0.18 μm CMOS process. The post simulation results show that the sampling rate is 5.12 MHz, the oversampling ratio is 128, and the signal bandwidth is 20 kHz for audio system. Moreover the signal-to-noise and distortion ratio(SNDR),the effective number of bit (ENOB),and the power consumption are 81 dB,13.32 bits, and 2.3 mW, respectively, with the supply voltage of 1.2V.

Topic Category 電資學院 > 電機工程系所
工程學 > 電機工程
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